linux-imx

// SPDX-License-Identifier: GPL-2.0+

//

// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.

​

#include <linux/init.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/rtc.h>

#include <linux/clk.h>

#include <linux/mfd/syscon.h>

#include <linux/regmap.h>

​

#define SNVS_LPREGISTER_OFFSET  0x34

​

/* These register offsets are relative to LP (Low Power) range */

#define SNVS_LPCR       0x04

#define SNVS_LPSR       0x18

#define SNVS_LPSRTCMR       0x1c

#define SNVS_LPSRTCLR       0x20

#define SNVS_LPTAR      0x24

#define SNVS_LPPGDR     0x30

​

#define SNVS_LPCR_SRTC_ENV  (1 << 0)

#define SNVS_LPCR_LPTA_EN   (1 << 1)

#define SNVS_LPCR_LPWUI_EN  (1 << 3)

#define SNVS_LPSR_LPTA      (1 << 0)

​

#define SNVS_LPPGDR_INIT    0x41736166

#define CNTR_TO_SECS_SH     15

​

struct snvs_rtc_data {

    struct rtc_device *rtc;

    struct regmap *regmap;

    int offset;

    int irq;

    struct clk *clk;

};

​

/* Read 64 bit timer register, which could be in inconsistent state */

static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)

{

    u32 msb, lsb;

​

    regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);

    regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);

    return (u64)msb << 32 | lsb;

}

​

/* Read the secure real time counter, taking care to deal with the cases of the

 * counter updating while being read.

 */

static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)

{

    u64 read1, read2;

    unsigned int timeout = 100;

​

    /* As expected, the registers might update between the read of the LSB

     * reg and the MSB reg.  It's also possible that one register might be

     * in partially modified state as well.