linux-imx

/*

 * APM X-Gene SoC Real Time Clock Driver

 *

 * Copyright (c) 2014, Applied Micro Circuits Corporation

 * Author: Rameshwar Prasad Sahu <rsahu@apm.com>

 *         Loc Ho <lho@apm.com>

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 *

 */

​

#include <linux/init.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/io.h>

#include <linux/slab.h>

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/rtc.h>

​

/* RTC CSR Registers */

#define RTC_CCVR        0x00

#define RTC_CMR         0x04

#define RTC_CLR         0x08

#define RTC_CCR         0x0C

#define  RTC_CCR_IE     BIT(0)

#define  RTC_CCR_MASK       BIT(1)

#define  RTC_CCR_EN     BIT(2)

#define  RTC_CCR_WEN        BIT(3)

#define RTC_STAT        0x10

#define  RTC_STAT_BIT       BIT(0)

#define RTC_RSTAT       0x14

#define RTC_EOI         0x18

#define RTC_VER         0x1C

​

struct xgene_rtc_dev {

    struct rtc_device *rtc;

    struct device *dev;

    unsigned long alarm_time;

    void __iomem *csr_base;

    struct clk *clk;

    unsigned int irq_wake;

    unsigned int irq_enabled;

};

​

static int xgene_rtc_read_time(struct device *dev, struct rtc_time *tm)

{

    struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);

​

    rtc_time_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);

    return 0;

}

​

static int xgene_rtc_set_mmss(struct device *dev, unsigned long secs)

{

    struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);

​

    /*

     * NOTE: After the following write, the RTC_CCVR is only reflected

     *       after the update cycle of 1 seconds.

     */

    writel((u32) secs, pdata->csr_base + RTC_CLR);

    readl(pdata->csr_base + RTC_CLR); /* Force a barrier */

​

    return 0;

}

​

static int xgene_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)

{

    struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);

​

    rtc_time_to_tm(pdata->alarm_time, &alrm->time);

    alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;

​

    return 0;

}

​

static int xgene_rtc_alarm_irq_enable(struct device *dev, u32 enabled)

{

    struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);