linux-imx

/* SPDX-License-Identifier: GPL-2.0 */

/* 

 * NCR 5380 defines

 *

 * Copyright 1993, Drew Eckhardt

 *  Visionary Computing

 *  (Unix consulting and custom programming)

 *  drew@colorado.edu

 *      +1 (303) 666-5836

 *

 * For more information, please consult 

 *

 * NCR 5380 Family

 * SCSI Protocol Controller

 * Databook

 * NCR Microelectronics

 * 1635 Aeroplaza Drive

 * Colorado Springs, CO 80916

 * 1+ (719) 578-3400

 * 1+ (800) 334-5454

 */

​

#ifndef NCR5380_H

#define NCR5380_H

​

#include <linux/delay.h>

#include <linux/interrupt.h>

#include <linux/list.h>

#include <linux/workqueue.h>

#include <scsi/scsi_dbg.h>

#include <scsi/scsi_eh.h>

#include <scsi/scsi_transport_spi.h>

​

#define NDEBUG_ARBITRATION  0x1

#define NDEBUG_AUTOSENSE    0x2

#define NDEBUG_DMA      0x4

#define NDEBUG_HANDSHAKE    0x8

#define NDEBUG_INFORMATION  0x10

#define NDEBUG_INIT     0x20

#define NDEBUG_INTR     0x40

#define NDEBUG_LINKED       0x80

#define NDEBUG_MAIN     0x100

#define NDEBUG_NO_DATAOUT   0x200

#define NDEBUG_NO_WRITE     0x400

#define NDEBUG_PIO      0x800

#define NDEBUG_PSEUDO_DMA   0x1000

#define NDEBUG_QUEUES       0x2000

#define NDEBUG_RESELECTION  0x4000

#define NDEBUG_SELECTION    0x8000

#define NDEBUG_USLEEP       0x10000

#define NDEBUG_LAST_BYTE_SENT   0x20000

#define NDEBUG_RESTART_SELECT   0x40000

#define NDEBUG_EXTENDED     0x80000

#define NDEBUG_C400_PREAD   0x100000

#define NDEBUG_C400_PWRITE  0x200000

#define NDEBUG_LISTS        0x400000

#define NDEBUG_ABORT        0x800000

#define NDEBUG_TAGS     0x1000000

#define NDEBUG_MERGING      0x2000000

​

#define NDEBUG_ANY      0xFFFFFFFFUL

​

/* 

 * The contents of the OUTPUT DATA register are asserted on the bus when

 * either arbitration is occurring or the phase-indicating signals (

 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA

 * bit in the INITIATOR COMMAND register is set.

 */

​

#define OUTPUT_DATA_REG         0   /* wo DATA lines on SCSI bus */

#define CURRENT_SCSI_DATA_REG   0   /* ro same */

​

#define INITIATOR_COMMAND_REG   1   /* rw */

#define ICR_ASSERT_RST      0x80    /* rw Set to assert RST  */

#define ICR_ARBITRATION_PROGRESS 0x40   /* ro Indicates arbitration complete */

#define ICR_TRI_STATE       0x40    /* wo Set to tri-state drivers */

#define ICR_ARBITRATION_LOST    0x20    /* ro Indicates arbitration lost */

#define ICR_DIFF_ENABLE     0x20    /* wo Set to enable diff. drivers */

#define ICR_ASSERT_ACK      0x10    /* rw ini Set to assert ACK */

#define ICR_ASSERT_BSY      0x08    /* rw Set to assert BSY */

#define ICR_ASSERT_SEL      0x04    /* rw Set to assert SEL */

#define ICR_ASSERT_ATN      0x02    /* rw Set to assert ATN */

#define ICR_ASSERT_DATA     0x01    /* rw SCSI_DATA_REG is asserted */

​

#define ICR_BASE        0

​

#define MODE_REG        2

/*

 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 

 * transfer, causing the chip to hog the bus.  You probably don't want 

 * this.

 */