linux-imx

/* SPDX-License-Identifier: GPL-2.0 */

/* esp_scsi.h: Defines and structures for the ESP driver.

 *

 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)

 */

​

#ifndef _ESP_SCSI_H

#define _ESP_SCSI_H

​

                    /* Access    Description      Offset */

#define ESP_TCLOW   0x00UL      /* rw  Low bits transfer count 0x00  */

#define ESP_TCMED   0x01UL      /* rw  Mid bits transfer count 0x04  */

#define ESP_FDATA   0x02UL      /* rw  FIFO data bits          0x08  */

#define ESP_CMD     0x03UL      /* rw  SCSI command bits       0x0c  */

#define ESP_STATUS  0x04UL      /* ro  ESP status register     0x10  */

#define ESP_BUSID   ESP_STATUS  /* wo  BusID for sel/resel     0x10  */

#define ESP_INTRPT  0x05UL      /* ro  Kind of interrupt       0x14  */

#define ESP_TIMEO   ESP_INTRPT  /* wo  Timeout for sel/resel   0x14  */

#define ESP_SSTEP   0x06UL      /* ro  Sequence step register  0x18  */

#define ESP_STP     ESP_SSTEP   /* wo  Transfer period/sync    0x18  */

#define ESP_FFLAGS  0x07UL      /* ro  Bits current FIFO info  0x1c  */

#define ESP_SOFF    ESP_FFLAGS  /* wo  Sync offset             0x1c  */

#define ESP_CFG1    0x08UL      /* rw  First cfg register      0x20  */

#define ESP_CFACT   0x09UL      /* wo  Clock conv factor       0x24  */

#define ESP_STATUS2 ESP_CFACT   /* ro  HME status2 register    0x24  */

#define ESP_CTEST   0x0aUL      /* wo  Chip test register      0x28  */

#define ESP_CFG2    0x0bUL      /* rw  Second cfg register     0x2c  */

#define ESP_CFG3    0x0cUL      /* rw  Third cfg register      0x30  */

#define ESP_CFG4    0x0dUL      /* rw  Fourth cfg register     0x34  */

#define ESP_TCHI    0x0eUL      /* rw  High bits transf count  0x38  */

#define ESP_UID     ESP_TCHI    /* ro  Unique ID code          0x38  */

#define FAS_RLO     ESP_TCHI    /* rw  HME extended counter    0x38  */

#define ESP_FGRND   0x0fUL      /* rw  Data base for fifo      0x3c  */

#define FAS_RHI     ESP_FGRND   /* rw  HME extended counter    0x3c  */

​

#define SBUS_ESP_REG_SIZE   0x40UL

​

/* Bitfield meanings for the above registers. */

​

/* ESP config reg 1, read-write, found on all ESP chips */

#define ESP_CONFIG1_ID        0x07      /* My BUS ID bits */

#define ESP_CONFIG1_CHTEST    0x08      /* Enable ESP chip tests */

#define ESP_CONFIG1_PENABLE   0x10      /* Enable parity checks */

#define ESP_CONFIG1_PARTEST   0x20      /* Parity test mode enabled? */

#define ESP_CONFIG1_SRRDISAB  0x40      /* Disable SCSI reset reports */

#define ESP_CONFIG1_SLCABLE   0x80      /* Enable slow cable mode */

​

/* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */

#define ESP_CONFIG2_DMAPARITY 0x01      /* enable DMA Parity (200,236) */

#define ESP_CONFIG2_REGPARITY 0x02      /* enable reg Parity (200,236) */

#define ESP_CONFIG2_BADPARITY 0x04      /* Bad parity target abort  */

#define ESP_CONFIG2_SCSI2ENAB 0x08      /* Enable SCSI-2 features (tgtmode) */

#define ESP_CONFIG2_HI        0x10      /* High Impedance DREQ ???  */

#define ESP_CONFIG2_HMEFENAB  0x10      /* HME features enable */

#define ESP_CONFIG2_BCM       0x20      /* Enable byte-ctrl (236)   */

#define ESP_CONFIG2_DISPINT   0x20      /* Disable pause irq (hme) */

#define ESP_CONFIG2_FENAB     0x40      /* Enable features (fas100,216) */

#define ESP_CONFIG2_SPL       0x40      /* Enable status-phase latch (236) */

#define ESP_CONFIG2_MKDONE    0x40      /* HME magic feature */

#define ESP_CONFIG2_HME32     0x80      /* HME 32 extended */

#define ESP_CONFIG2_MAGIC     0xe0      /* Invalid bits... */

​

/* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */