linux-imx

/*

 * Marvell 88SE94xx hardware specific head file

 *

 * Copyright 2007 Red Hat, Inc.

 * Copyright 2008 Marvell. <kewei@marvell.com>

 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>

 *

 * This file is licensed under GPLv2.

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; version 2 of the

 * License.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307

 * USA

*/

​

#ifndef _MVS94XX_REG_H_

#define _MVS94XX_REG_H_

​

#include <linux/types.h>

​

#define MAX_LINK_RATE       SAS_LINK_RATE_6_0_GBPS

​

enum VANIR_REVISION_ID {

    VANIR_A0_REV        = 0xA0,

    VANIR_B0_REV        = 0x01,

    VANIR_C0_REV        = 0x02,

    VANIR_C1_REV        = 0x03,

    VANIR_C2_REV        = 0xC2,

};

​

enum host_registers {

    MVS_HST_CHIP_CONFIG = 0x10104,  /* chip configuration */

};

​

enum hw_registers {

    MVS_GBL_CTL     = 0x04,  /* global control */

    MVS_GBL_INT_STAT    = 0x00,  /* global irq status */

    MVS_GBL_PI      = 0x0C,  /* ports implemented bitmask */

​

    MVS_PHY_CTL     = 0x40,  /* SOC PHY Control */

    MVS_PORTS_IMP       = 0x9C,  /* SOC Port Implemented */

​

    MVS_GBL_PORT_TYPE   = 0xa0,  /* port type */

​

    MVS_CTL         = 0x100, /* SAS/SATA port configuration */

    MVS_PCS         = 0x104, /* SAS/SATA port control/status */

    MVS_CMD_LIST_LO     = 0x108, /* cmd list addr */

    MVS_CMD_LIST_HI     = 0x10C,

    MVS_RX_FIS_LO       = 0x110, /* RX FIS list addr */

    MVS_RX_FIS_HI       = 0x114,

    MVS_STP_REG_SET_0   = 0x118, /* STP/SATA Register Set Enable */

    MVS_STP_REG_SET_1   = 0x11C,

    MVS_TX_CFG      = 0x120, /* TX configuration */

    MVS_TX_LO       = 0x124, /* TX (delivery) ring addr */

    MVS_TX_HI       = 0x128,

​

    MVS_TX_PROD_IDX     = 0x12C, /* TX producer pointer */

    MVS_TX_CONS_IDX     = 0x130, /* TX consumer pointer (RO) */

    MVS_RX_CFG      = 0x134, /* RX configuration */

    MVS_RX_LO       = 0x138, /* RX (completion) ring addr */

    MVS_RX_HI       = 0x13C,

    MVS_RX_CONS_IDX     = 0x140, /* RX consumer pointer (RO) */

​

    MVS_INT_COAL        = 0x148, /* Int coalescing config */

    MVS_INT_COAL_TMOUT  = 0x14C, /* Int coalescing timeout */

    MVS_INT_STAT        = 0x150, /* Central int status */

    MVS_INT_MASK        = 0x154, /* Central int enable */

    MVS_INT_STAT_SRS_0  = 0x158, /* SATA register set status */

    MVS_INT_MASK_SRS_0  = 0x15C,

    MVS_INT_STAT_SRS_1  = 0x160,

    MVS_INT_MASK_SRS_1  = 0x164,

    MVS_NON_NCQ_ERR_0   = 0x168, /* SRS Non-specific NCQ Error */

    MVS_NON_NCQ_ERR_1   = 0x16C,

    MVS_CMD_ADDR        = 0x170, /* Command register port (addr) */

    MVS_CMD_DATA        = 0x174, /* Command register port (data) */

    MVS_MEM_PARITY_ERR  = 0x178, /* Memory parity error */

​

                     /* ports 1-3 follow after this */

    MVS_P0_INT_STAT     = 0x180, /* port0 interrupt status */

    MVS_P0_INT_MASK     = 0x184, /* port0 interrupt mask */

                     /* ports 5-7 follow after this */

    MVS_P4_INT_STAT     = 0x1A0, /* Port4 interrupt status */