linux-imx

/*

 * Marvell 88SE64xx/88SE94xx register IO interface

 *

 * Copyright 2007 Red Hat, Inc.

 * Copyright 2008 Marvell. <kewei@marvell.com>

 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>

 *

 * This file is licensed under GPLv2.

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; version 2 of the

 * License.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307

 * USA

*/

​

​

#ifndef _MV_CHIPS_H_

#define _MV_CHIPS_H_

​

#define mr32(reg)   readl(regs + reg)

#define mw32(reg, val)  writel((val), regs + reg)

#define mw32_f(reg, val)    do {            \

                mw32(reg, val); \

                mr32(reg);  \

            } while (0)

​

#define iow32(reg, val)     outl(val, (unsigned long)(regs + reg))

#define ior32(reg)      inl((unsigned long)(regs + reg))

#define iow16(reg, val)     outw((unsigned long)(val, regs + reg))

#define ior16(reg)      inw((unsigned long)(regs + reg))

#define iow8(reg, val)      outb((unsigned long)(val, regs + reg))

#define ior8(reg)       inb((unsigned long)(regs + reg))

​

static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)

{

    void __iomem *regs = mvi->regs;

    mw32(MVS_CMD_ADDR, addr);

    return mr32(MVS_CMD_DATA);

}

​

static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)

{

    void __iomem *regs = mvi->regs;

    mw32(MVS_CMD_ADDR, addr);

    mw32(MVS_CMD_DATA, val);

}

​

static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)

{

    void __iomem *regs = mvi->regs;

    return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :

        mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);

}

​

static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)

{

    void __iomem *regs = mvi->regs;

    if (port < 4)

        mw32(MVS_P0_SER_CTLSTAT + port * 4, val);

    else

        mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);

}

​

static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,

                u32 off2, u32 port)

{

    void __iomem *regs = mvi->regs + off;

    void __iomem *regs2 = mvi->regs + off2;

    return (port < 4) ? readl(regs + port * 8) :

        readl(regs2 + (port - 4) * 8);

}

​

static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,

                u32 port, u32 val)

{

    void __iomem *regs = mvi->regs + off;

    void __iomem *regs2 = mvi->regs + off2;

    if (port < 4)

        writel(val, regs + port * 8);

    else

        writel(val, regs2 + (port - 4) * 8);

}