linux-imx

/*

 *    driver for Microsemi PQI-based storage controllers

 *    Copyright (c) 2016-2017 Microsemi Corporation

 *    Copyright (c) 2016 PMC-Sierra, Inc.

 *

 *    This program is free software; you can redistribute it and/or modify

 *    it under the terms of the GNU General Public License as published by

 *    the Free Software Foundation; version 2 of the License.

 *

 *    This program is distributed in the hope that it will be useful,

 *    but WITHOUT ANY WARRANTY; without even the implied warranty of

 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or

 *    NON INFRINGEMENT.  See the GNU General Public License for more details.

 *

 *    Questions/Comments/Bugfixes to esc.storagedev@microsemi.com

 *

 */

​

#include <linux/io-64-nonatomic-lo-hi.h>

​

#if !defined(_SMARTPQI_H)

#define _SMARTPQI_H

​

#include <scsi/scsi_host.h>

#include <linux/bsg-lib.h>

​

#pragma pack(1)

​

#define PQI_DEVICE_SIGNATURE    "PQI DREG"

​

/* This structure is defined by the PQI specification. */

struct pqi_device_registers {

    __le64  signature;

    u8  function_and_status_code;

    u8  reserved[7];

    u8  max_admin_iq_elements;

    u8  max_admin_oq_elements;

    u8  admin_iq_element_length;    /* in 16-byte units */

    u8  admin_oq_element_length;    /* in 16-byte units */

    __le16  max_reset_timeout;      /* in 100-millisecond units */

    u8  reserved1[2];

    __le32  legacy_intx_status;

    __le32  legacy_intx_mask_set;

    __le32  legacy_intx_mask_clear;

    u8  reserved2[28];

    __le32  device_status;

    u8  reserved3[4];

    __le64  admin_iq_pi_offset;

    __le64  admin_oq_ci_offset;

    __le64  admin_iq_element_array_addr;

    __le64  admin_oq_element_array_addr;

    __le64  admin_iq_ci_addr;

    __le64  admin_oq_pi_addr;

    u8  admin_iq_num_elements;

    u8  admin_oq_num_elements;

    __le16  admin_queue_int_msg_num;

    u8  reserved4[4];

    __le32  device_error;

    u8  reserved5[4];

    __le64  error_details;

    __le32  device_reset;

    __le32  power_action;

    u8  reserved6[104];

};

​

/*

 * controller registers

 *

 * These are defined by the Microsemi implementation.

 *

 * Some registers (those named sis_*) are only used when in

 * legacy SIS mode before we transition the controller into

 * PQI mode.  There are a number of other SIS mode registers,

 * but we don't use them, so only the SIS registers that we

 * care about are defined here.  The offsets mentioned in the

 * comments are the offsets from the PCIe BAR 0.

 */

struct pqi_ctrl_registers {

    u8  reserved[0x20];

    __le32  sis_host_to_ctrl_doorbell;      /* 20h */

    u8  reserved1[0x34 - (0x20 + sizeof(__le32))];

    __le32  sis_interrupt_mask;         /* 34h */

    u8  reserved2[0x9c - (0x34 + sizeof(__le32))];

    __le32  sis_ctrl_to_host_doorbell;      /* 9Ch */

    u8  reserved3[0xa0 - (0x9c + sizeof(__le32))];

    __le32  sis_ctrl_to_host_doorbell_clear;    /* A0h */

    u8  reserved4[0xb0 - (0xa0 + sizeof(__le32))];

    __le32  sis_driver_scratch;         /* B0h */

    u8  reserved5[0xbc - (0xb0 + sizeof(__le32))];

    __le32  sis_firmware_status;            /* BCh */

    u8  reserved6[0x1000 - (0xbc + sizeof(__le32))];

    __le32  sis_mailbox[8];             /* 1000h */