linux-imx

// SPDX-License-Identifier: GPL-2.0

//

// Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.

//      http://www.samsung.com/

//

// EXYNOS5250 - CPU PMU (Power Management Unit) support

​

#include <linux/soc/samsung/exynos-regs-pmu.h>

#include <linux/soc/samsung/exynos-pmu.h>

​

#include "exynos-pmu.h"

​

static const struct exynos_pmu_conf exynos5250_pmu_config[] = {

    /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */

    { EXYNOS5_ARM_CORE0_SYS_PWR_REG,        { 0x0, 0x0, 0x2} },

    { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },

    { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },

    { EXYNOS5_ARM_CORE1_SYS_PWR_REG,        { 0x0, 0x0, 0x2} },

    { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },

    { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },

    { EXYNOS5_FSYS_ARM_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },

    { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },

    { EXYNOS5_ISP_ARM_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },

    { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0} },

    { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },

    { EXYNOS5_ARM_COMMON_SYS_PWR_REG,       { 0x0, 0x0, 0x2} },

    { EXYNOS5_ARM_L2_SYS_PWR_REG,           { 0x3, 0x3, 0x3} },

    { EXYNOS_L2_OPTION(0),              { 0x10, 0x10, 0x0 } },

    { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,     { 0x1, 0x0, 0x1} },

    { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,     { 0x1, 0x0, 0x1} },

    { EXYNOS5_CMU_RESET_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },

    { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,  { 0x1, 0x0, 0x1} },

    { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,  { 0x1, 0x0, 0x1} },

    { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,     { 0x1, 0x1, 0x0} },

    { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,       { 0x1, 0x1, 0x1} },

    { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,        { 0x1, 0x1, 0x1} },

    { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,       { 0x1, 0x1, 0x1} },

    { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },

    { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },

    { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },

    { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x1, 0x0} },

    { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },

    { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },

    { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },

    { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },

    { EXYNOS5_TOP_BUS_SYS_PWR_REG,          { 0x3, 0x0, 0x0} },

    { EXYNOS5_TOP_RETENTION_SYS_PWR_REG,        { 0x1, 0x0, 0x1} },

    { EXYNOS5_TOP_PWR_SYS_PWR_REG,          { 0x3, 0x0, 0x3} },

    { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,       { 0x3, 0x0, 0x0} },

    { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },

    { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,       { 0x3, 0x0, 0x3} },

    { EXYNOS5_LOGIC_RESET_SYS_PWR_REG,      { 0x1, 0x1, 0x0} },

    { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,      { 0x1, 0x0, 0x1} },

    { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },

    { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,   { 0x1, 0x0, 0x1} },

    { EXYNOS5_USBOTG_MEM_SYS_PWR_REG,       { 0x3, 0x0, 0x0} },

    { EXYNOS5_G2D_MEM_SYS_PWR_REG,          { 0x3, 0x0, 0x0} },

    { EXYNOS5_USBDRD_MEM_SYS_PWR_REG,       { 0x3, 0x0, 0x0} },

    { EXYNOS5_SDMMC_MEM_SYS_PWR_REG,        { 0x3, 0x0, 0x0} },

    { EXYNOS5_CSSYS_MEM_SYS_PWR_REG,        { 0x3, 0x0, 0x0} },

    { EXYNOS5_SECSS_MEM_SYS_PWR_REG,        { 0x3, 0x0, 0x0} },

    { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG,      { 0x3, 0x0, 0x0} },

    { EXYNOS5_INTRAM_MEM_SYS_PWR_REG,       { 0x3, 0x0, 0x0} },