linux-imx

// SPDX-License-Identifier: GPL-2.0-only

/*

 * AMx3 Wkup M3 IPC driver

 *

 * Copyright (C) 2015 Texas Instruments, Inc.

 *

 * Dave Gerlach <d-gerlach@ti.com>

 */

​

#include <linux/err.h>

#include <linux/kernel.h>

#include <linux/kthread.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/omap-mailbox.h>

#include <linux/platform_device.h>

#include <linux/remoteproc.h>

#include <linux/suspend.h>

#include <linux/wkup_m3_ipc.h>

​

#define AM33XX_CTRL_IPC_REG_COUNT   0x8

#define AM33XX_CTRL_IPC_REG_OFFSET(m)   (0x4 + 4 * (m))

​

/* AM33XX M3_TXEV_EOI register */

#define AM33XX_CONTROL_M3_TXEV_EOI  0x00

​

#define AM33XX_M3_TXEV_ACK      (0x1 << 0)

#define AM33XX_M3_TXEV_ENABLE       (0x0 << 0)

​

#define IPC_CMD_DS0         0x4

#define IPC_CMD_STANDBY         0xc

#define IPC_CMD_IDLE            0x10

#define IPC_CMD_RESET           0xe

#define DS_IPC_DEFAULT          0xffffffff

#define M3_VERSION_UNKNOWN      0x0000ffff

#define M3_BASELINE_VERSION     0x191

#define M3_STATUS_RESP_MASK     (0xffff << 16)

#define M3_FW_VERSION_MASK      0xffff

#define M3_WAKE_SRC_MASK        0xff

​

#define M3_STATE_UNKNOWN        0

#define M3_STATE_RESET          1

#define M3_STATE_INITED         2

#define M3_STATE_MSG_FOR_LP     3

#define M3_STATE_MSG_FOR_RESET      4

​

static struct wkup_m3_ipc *m3_ipc_state;

​

static const struct wkup_m3_wakeup_src wakeups[] = {

    {.irq_nr = 16,  .src = "PRCM"},

    {.irq_nr = 35,  .src = "USB0_PHY"},

    {.irq_nr = 36,  .src = "USB1_PHY"},

    {.irq_nr = 40,  .src = "I2C0"},

    {.irq_nr = 41,  .src = "RTC Timer"},

    {.irq_nr = 42,  .src = "RTC Alarm"},

    {.irq_nr = 43,  .src = "Timer0"},

    {.irq_nr = 44,  .src = "Timer1"},

    {.irq_nr = 45,  .src = "UART"},

    {.irq_nr = 46,  .src = "GPIO0"},

    {.irq_nr = 48,  .src = "MPU_WAKE"},

    {.irq_nr = 49,  .src = "WDT0"},

    {.irq_nr = 50,  .src = "WDT1"},

    {.irq_nr = 51,  .src = "ADC_TSC"},

    {.irq_nr = 0,   .src = "Unknown"},

};

​

static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)

{

    writel(AM33XX_M3_TXEV_ACK,

           m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);

}

​

static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc)

{

    writel(AM33XX_M3_TXEV_ENABLE,

           m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);

}

​

static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc,

                   u32 val, int ipc_reg_num)

{

    if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,

         "ipc register operation out of range"))

        return;

​

    writel(val, m3_ipc->ipc_mem_base +

           AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));

}

​

static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc,