linux-imx

/*

 * Driver for Broadcom BRCMSTB, NSP,  NS2, Cygnus SPI Controllers

 *

 * Copyright 2016 Broadcom

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License, version 2, as

 * published by the Free Software Foundation (the "GPL").

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License version 2 (GPLv2) for more details.

 *

 * You should have received a copy of the GNU General Public License

 * version 2 (GPLv2) along with this source code.

 */

​

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/device.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/ioport.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_irq.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include <linux/spi/spi.h>

#include <linux/spi/spi-mem.h>

#include <linux/sysfs.h>

#include <linux/types.h>

#include "spi-bcm-qspi.h"

​

#define DRIVER_NAME "bcm_qspi"

​

​

/* BSPI register offsets */

#define BSPI_REVISION_ID            0x000

#define BSPI_SCRATCH                0x004

#define BSPI_MAST_N_BOOT_CTRL           0x008

#define BSPI_BUSY_STATUS            0x00c

#define BSPI_INTR_STATUS            0x010

#define BSPI_B0_STATUS              0x014

#define BSPI_B0_CTRL                0x018

#define BSPI_B1_STATUS              0x01c

#define BSPI_B1_CTRL                0x020

#define BSPI_STRAP_OVERRIDE_CTRL        0x024

#define BSPI_FLEX_MODE_ENABLE           0x028

#define BSPI_BITS_PER_CYCLE         0x02c

#define BSPI_BITS_PER_PHASE         0x030

#define BSPI_CMD_AND_MODE_BYTE          0x034

#define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038

#define BSPI_BSPI_XOR_VALUE         0x03c

#define BSPI_BSPI_XOR_ENABLE            0x040

#define BSPI_BSPI_PIO_MODE_ENABLE       0x044

#define BSPI_BSPI_PIO_IODIR         0x048

#define BSPI_BSPI_PIO_DATA          0x04c

​

/* RAF register offsets */