linux-imx

/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __SPI_CAVIUM_H

#define __SPI_CAVIUM_H

​

#include <linux/clk.h>

​

#define OCTEON_SPI_MAX_BYTES 9

#define OCTEON_SPI_MAX_CLOCK_HZ 16000000

​

struct octeon_spi_regs {

    int config;

    int status;

    int tx;

    int data;

};

​

struct octeon_spi {

    void __iomem *register_base;

    u64 last_cfg;

    u64 cs_enax;

    int sys_freq;

    struct octeon_spi_regs regs;

    struct clk *clk;

};

​

#define OCTEON_SPI_CFG(x)   (x->regs.config)

#define OCTEON_SPI_STS(x)   (x->regs.status)

#define OCTEON_SPI_TX(x)    (x->regs.tx)

#define OCTEON_SPI_DAT0(x)  (x->regs.data)

​

int octeon_spi_transfer_one_message(struct spi_master *master,

                    struct spi_message *msg);

​

/* MPI register descriptions */

​

#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))

#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)

#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))

#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))

​

union cvmx_mpi_cfg {

    uint64_t u64;

    struct cvmx_mpi_cfg_s {

#ifdef __BIG_ENDIAN_BITFIELD

        uint64_t reserved_29_63:35;

        uint64_t clkdiv:13;

        uint64_t csena3:1;

        uint64_t csena2:1;

        uint64_t csena1:1;

        uint64_t csena0:1;

        uint64_t cslate:1;

        uint64_t tritx:1;

        uint64_t idleclks:2;

        uint64_t cshi:1;

        uint64_t csena:1;

        uint64_t int_ena:1;

        uint64_t lsbfirst:1;

        uint64_t wireor:1;

        uint64_t clk_cont:1;

        uint64_t idlelo:1;

        uint64_t enable:1;

#else

        uint64_t enable:1;

        uint64_t idlelo:1;

        uint64_t clk_cont:1;

        uint64_t wireor:1;

        uint64_t lsbfirst:1;

        uint64_t int_ena:1;

        uint64_t csena:1;

        uint64_t cshi:1;

        uint64_t idleclks:2;

        uint64_t tritx:1;

        uint64_t cslate:1;

        uint64_t csena0:1;

        uint64_t csena1:1;

        uint64_t csena2:1;

        uint64_t csena3:1;

        uint64_t clkdiv:13;

        uint64_t reserved_29_63:35;

#endif

    } s;

    struct cvmx_mpi_cfg_cn30xx {

#ifdef __BIG_ENDIAN_BITFIELD

        uint64_t reserved_29_63:35;

        uint64_t clkdiv:13;

        uint64_t reserved_12_15:4;

        uint64_t cslate:1;

        uint64_t tritx:1;

        uint64_t idleclks:2;

        uint64_t cshi:1;

        uint64_t csena:1;

        uint64_t int_ena:1;