linux-imx

/*

 * Freescale eSPI controller driver.

 *

 * Copyright 2010 Freescale Semiconductor, Inc.

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/fsl_devices.h>

#include <linux/interrupt.h>

#include <linux/module.h>

#include <linux/mm.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

#include <linux/of_platform.h>

#include <linux/platform_device.h>

#include <linux/spi/spi.h>

#include <linux/pm_runtime.h>

#include <sysdev/fsl_soc.h>

​

/* eSPI Controller registers */

#define ESPI_SPMODE 0x00    /* eSPI mode register */

#define ESPI_SPIE   0x04    /* eSPI event register */

#define ESPI_SPIM   0x08    /* eSPI mask register */

#define ESPI_SPCOM  0x0c    /* eSPI command register */

#define ESPI_SPITF  0x10    /* eSPI transmit FIFO access register*/

#define ESPI_SPIRF  0x14    /* eSPI receive FIFO access register*/

#define ESPI_SPMODE0    0x20    /* eSPI cs0 mode register */

​

#define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)

​

/* eSPI Controller mode register definitions */

#define SPMODE_ENABLE       BIT(31)

#define SPMODE_LOOP     BIT(30)

#define SPMODE_TXTHR(x)     ((x) << 8)

#define SPMODE_RXTHR(x)     ((x) << 0)

​

/* eSPI Controller CS mode register definitions */

#define CSMODE_CI_INACTIVEHIGH  BIT(31)

#define CSMODE_CP_BEGIN_EDGECLK BIT(30)

#define CSMODE_REV      BIT(29)

#define CSMODE_DIV16        BIT(28)

#define CSMODE_PM(x)        ((x) << 24)

#define CSMODE_POL_1        BIT(20)

#define CSMODE_LEN(x)       ((x) << 16)

#define CSMODE_BEF(x)       ((x) << 12)

#define CSMODE_AFT(x)       ((x) << 8)

#define CSMODE_CG(x)        ((x) << 3)

​

#define FSL_ESPI_FIFO_SIZE  32

#define FSL_ESPI_RXTHR      15

​

/* Default mode/csmode for eSPI controller */

#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR))

#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \

        | CSMODE_AFT(0) | CSMODE_CG(1))

​

/* SPIE register values */

#define SPIE_RXCNT(reg)     ((reg >> 24) & 0x3F)

#define SPIE_TXCNT(reg)     ((reg >> 16) & 0x3F)

#define SPIE_TXE        BIT(15) /* TX FIFO empty */

#define SPIE_DON        BIT(14) /* TX done */

#define SPIE_RXT        BIT(13) /* RX FIFO threshold */

#define SPIE_RXF        BIT(12) /* RX FIFO full */

#define SPIE_TXT        BIT(11) /* TX FIFO threshold*/

#define SPIE_RNE        BIT(9)  /* RX FIFO not empty */

#define SPIE_TNF        BIT(8)  /* TX FIFO not full */

​

/* SPIM register values */

#define SPIM_TXE        BIT(15) /* TX FIFO empty */

#define SPIM_DON        BIT(14) /* TX done */

#define SPIM_RXT        BIT(13) /* RX FIFO threshold */

#define SPIM_RXF        BIT(12) /* RX FIFO full */

#define SPIM_TXT        BIT(11) /* TX FIFO threshold*/

#define SPIM_RNE        BIT(9)  /* RX FIFO not empty */

#define SPIM_TNF        BIT(8)  /* TX FIFO not full */

​

/* SPCOM register values */

#define SPCOM_CS(x)     ((x) << 30)

#define SPCOM_DO        BIT(28) /* Dual output */

#define SPCOM_TO        BIT(27) /* TX only */

#define SPCOM_RXSKIP(x)     ((x) << 16)

#define SPCOM_TRANLEN(x)    ((x) << 0)

​

#define SPCOM_TRANLEN_MAX   0x10000 /* Max transaction length */

​

#define AUTOSUSPEND_TIMEOUT 2000