linux-imx

/*

 * J-Core SPI controller driver

 *

 * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.

 *

 * Current version by Rich Felker

 * Based loosely on initial version by Oleksandr G Zhadan

 *

 */

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/errno.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/spi/spi.h>

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/delay.h>

​

#define DRV_NAME    "jcore_spi"

​

#define CTRL_REG    0x0

#define DATA_REG    0x4

​

#define JCORE_SPI_CTRL_XMIT     0x02

#define JCORE_SPI_STAT_BUSY     0x02

#define JCORE_SPI_CTRL_LOOP     0x08

#define JCORE_SPI_CTRL_CS_BITS      0x15

​

#define JCORE_SPI_WAIT_RDY_MAX_LOOP 2000000

​

struct jcore_spi {

    struct spi_master *master;

    void __iomem *base;

    unsigned int cs_reg;

    unsigned int speed_reg;

    unsigned int speed_hz;

    unsigned int clock_freq;

};

​

static int jcore_spi_wait(void __iomem *ctrl_reg)

{

    unsigned timeout = JCORE_SPI_WAIT_RDY_MAX_LOOP;

​

    do {

        if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY))

            return 0;

        cpu_relax();

    } while (--timeout);

​

    return -EBUSY;

}

​

static void jcore_spi_program(struct jcore_spi *hw)

{

    void __iomem *ctrl_reg = hw->base + CTRL_REG;

​

    if (jcore_spi_wait(ctrl_reg))

        dev_err(hw->master->dev.parent,

            "timeout waiting to program ctrl reg.\n");

​

    writel(hw->cs_reg | hw->speed_reg, ctrl_reg);

}

​

static void jcore_spi_chipsel(struct spi_device *spi, bool value)

{

    struct jcore_spi *hw = spi_master_get_devdata(spi->master);

    u32 csbit = 1U << (2 * spi->chip_select);

​

    dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi->chip_select);

​

    if (value)

        hw->cs_reg |= csbit;

    else

        hw->cs_reg &= ~csbit;

​

    jcore_spi_program(hw);

}

​

static void jcore_spi_baudrate(struct jcore_spi *hw, int speed)

{

    if (speed == hw->speed_hz) return;

    hw->speed_hz = speed;

    if (speed >= hw->clock_freq / 2)

        hw->speed_reg = 0;

    else

        hw->speed_reg = ((hw->clock_freq / 2 / speed) - 1) << 27;

    jcore_spi_program(hw);

    dev_dbg(hw->master->dev.parent, "speed=%d reg=0x%x\n",

        speed, hw->speed_reg);