linux-imx

/*

 * Driver for LM70EVAL-LLP board for the LM70 sensor

 *

 * Copyright (C) 2006 Kaiwan N Billimoria <kaiwan@designergraphix.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

​

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

​

#include <linux/init.h>

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/delay.h>

#include <linux/device.h>

#include <linux/parport.h>

#include <linux/sysfs.h>

#include <linux/workqueue.h>

​

#include <linux/spi/spi.h>

#include <linux/spi/spi_bitbang.h>

​

/*

 * The LM70 communicates with a host processor using a 3-wire variant of

 * the SPI/Microwire bus interface. This driver specifically supports an

 * NS LM70 LLP Evaluation Board, interfacing to a PC using its parallel

 * port to bitbang an SPI-parport bridge.  Accordingly, this is an SPI

 * master controller driver.  The hwmon/lm70 driver is a "SPI protocol

 * driver", layered on top of this one and usable without the lm70llp.

 *

 * Datasheet and Schematic:

 * The LM70 is a temperature sensor chip from National Semiconductor; its

 * datasheet is available at http://www.national.com/pf/LM/LM70.html

 * The schematic for this particular board (the LM70EVAL-LLP) is

 * available (on page 4) here:

 *  http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf

 *

 * Also see Documentation/spi/spi-lm70llp.  The SPI<->parport code here is

 * (heavily) based on spi-butterfly by David Brownell.

 *

 * The LM70 LLP connects to the PC parallel port in the following manner:

 *

 *   Parallel                 LM70 LLP

 *     Port      Direction   JP2 Header

 *  -----------  ---------  ------------

 *      D0    2      -         -

 *      D1    3     -->      V+   5

 *      D2    4     -->      V+   5

 *      D3    5     -->      V+   5

 *      D4    6     -->      V+   5

 *      D5    7     -->      nCS  8

 *      D6    8     -->      SCLK 3

 *      D7    9     -->      SI/O 5

 *     GND   25      -       GND  7

 *    Select 13     <--      SI/O 1