linux-imx

/*

 * Copyright (c) 2015 MediaTek Inc.

 * Author: Leilk Liu <leilk.liu@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

​

#include <linux/clk.h>

#include <linux/device.h>

#include <linux/err.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/ioport.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_gpio.h>

#include <linux/platform_device.h>

#include <linux/platform_data/spi-mt65xx.h>

#include <linux/pm_runtime.h>

#include <linux/spi/spi.h>

​

#define SPI_CFG0_REG                      0x0000

#define SPI_CFG1_REG                      0x0004

#define SPI_TX_SRC_REG                    0x0008

#define SPI_RX_DST_REG                    0x000c

#define SPI_TX_DATA_REG                   0x0010

#define SPI_RX_DATA_REG                   0x0014

#define SPI_CMD_REG                       0x0018

#define SPI_STATUS0_REG                   0x001c

#define SPI_PAD_SEL_REG                   0x0024

#define SPI_CFG2_REG                      0x0028

​

#define SPI_CFG0_SCK_HIGH_OFFSET          0

#define SPI_CFG0_SCK_LOW_OFFSET           8

#define SPI_CFG0_CS_HOLD_OFFSET           16

#define SPI_CFG0_CS_SETUP_OFFSET          24

#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET    16

#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET    0

#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET   16

​

#define SPI_CFG1_CS_IDLE_OFFSET           0

#define SPI_CFG1_PACKET_LOOP_OFFSET       8

#define SPI_CFG1_PACKET_LENGTH_OFFSET     16

#define SPI_CFG1_GET_TICK_DLY_OFFSET      30

​

#define SPI_CFG1_CS_IDLE_MASK             0xff

#define SPI_CFG1_PACKET_LOOP_MASK         0xff00

#define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000

​

#define SPI_CMD_ACT                  BIT(0)

#define SPI_CMD_RESUME               BIT(1)

#define SPI_CMD_RST                  BIT(2)

#define SPI_CMD_PAUSE_EN             BIT(4)

#define SPI_CMD_DEASSERT             BIT(5)

#define SPI_CMD_SAMPLE_SEL           BIT(6)

#define SPI_CMD_CS_POL               BIT(7)

#define SPI_CMD_CPHA                 BIT(8)

#define SPI_CMD_CPOL                 BIT(9)

#define SPI_CMD_RX_DMA               BIT(10)

#define SPI_CMD_TX_DMA               BIT(11)

#define SPI_CMD_TXMSBF               BIT(12)

#define SPI_CMD_RXMSBF               BIT(13)

#define SPI_CMD_RX_ENDIAN            BIT(14)

#define SPI_CMD_TX_ENDIAN            BIT(15)

#define SPI_CMD_FINISH_IE            BIT(16)

#define SPI_CMD_PAUSE_IE             BIT(17)

​

#define MT8173_SPI_MAX_PAD_SEL 3

​

#define MTK_SPI_PAUSE_INT_STATUS 0x2

​

#define MTK_SPI_IDLE 0

#define MTK_SPI_PAUSED 1

​

#define MTK_SPI_MAX_FIFO_SIZE 32U

#define MTK_SPI_PACKET_SIZE 1024

​

struct mtk_spi_compatible {

    bool need_pad_sel;

    /* Must explicitly send dummy Tx bytes to do Rx only transfer */

    bool must_tx;

    /* some IC design adjust cfg register to enhance time accuracy */

    bool enhance_timing;

};

​