linux-imx

// SPDX-License-Identifier: GPL-2.0

//

// spi-mt7621.c -- MediaTek MT7621 SPI controller driver

//

// Copyright (C) 2011 Sergiy <piratfm@gmail.com>

// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>

// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>

//

// Some parts are based on spi-orion.c:

//   Author: Shadi Ammouri <shadi@marvell.com>

//   Copyright (C) 2007-2008 Marvell Ltd.

​

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/of_device.h>

#include <linux/reset.h>

#include <linux/spi/spi.h>

​

#define DRIVER_NAME     "spi-mt7621"

​

/* in usec */

#define RALINK_SPI_WAIT_MAX_LOOP 2000

​

/* SPISTAT register bit field */

#define SPISTAT_BUSY        BIT(0)

​

#define MT7621_SPI_TRANS    0x00

#define SPITRANS_BUSY       BIT(16)

​

#define MT7621_SPI_OPCODE   0x04

#define MT7621_SPI_DATA0    0x08

#define MT7621_SPI_DATA4    0x18

#define SPI_CTL_TX_RX_CNT_MASK  0xff

#define SPI_CTL_START       BIT(8)

​

#define MT7621_SPI_MASTER   0x28

#define MASTER_MORE_BUFMODE BIT(2)

#define MASTER_FULL_DUPLEX  BIT(10)

#define MASTER_RS_CLK_SEL   GENMASK(27, 16)

#define MASTER_RS_CLK_SEL_SHIFT 16

#define MASTER_RS_SLAVE_SEL GENMASK(31, 29)

​

#define MT7621_SPI_MOREBUF  0x2c

#define MT7621_SPI_POLAR    0x38

#define MT7621_SPI_SPACE    0x3c

​

#define MT7621_CPHA     BIT(5)

#define MT7621_CPOL     BIT(4)

#define MT7621_LSB_FIRST    BIT(3)

​

struct mt7621_spi {

    struct spi_controller   *master;

    void __iomem        *base;

    unsigned int        sys_freq;

    unsigned int        speed;

    struct clk      *clk;

    int         pending_write;

};

​

static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)

{

    return spi_controller_get_devdata(spi->master);

}

​

static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)

{

    return ioread32(rs->base + reg);

}

​

static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)

{

    iowrite32(val, rs->base + reg);

}

​

static void mt7621_spi_set_cs(struct spi_device *spi, int enable)

{

    struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);

    int cs = spi->chip_select;

    u32 polar = 0;

    u32 master;

​

    /*

     * Select SPI device 7, enable "more buffer mode" and disable

     * full-duplex (only half-duplex really works on this chip

     * reliably)

     */

    master = mt7621_spi_read(rs, MT7621_SPI_MASTER);

    master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;

    master &= ~MASTER_FULL_DUPLEX;

    mt7621_spi_write(rs, MT7621_SPI_MASTER, master);