linux-imx

/*

 * PIC32 Quad SPI controller driver.

 *

 * Purna Chandra Mandal <purna.mandal@microchip.com>

 * Copyright (c) 2016, Microchip Technology Inc.

 *

 * This program is free software; you can distribute it and/or modify it

 * under the terms of the GNU General Public License (Version 2) as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * for more details.

 */

​

#include <linux/clk.h>

#include <linux/dma-mapping.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include <linux/spi/spi.h>

​

/* SQI registers */

#define PESQI_XIP_CONF1_REG 0x00

#define PESQI_XIP_CONF2_REG 0x04

#define PESQI_CONF_REG      0x08

#define PESQI_CTRL_REG      0x0C

#define PESQI_CLK_CTRL_REG  0x10

#define PESQI_CMD_THRES_REG 0x14

#define PESQI_INT_THRES_REG 0x18

#define PESQI_INT_ENABLE_REG    0x1C

#define PESQI_INT_STAT_REG  0x20

#define PESQI_TX_DATA_REG   0x24

#define PESQI_RX_DATA_REG   0x28

#define PESQI_STAT1_REG     0x2C

#define PESQI_STAT2_REG     0x30

#define PESQI_BD_CTRL_REG   0x34

#define PESQI_BD_CUR_ADDR_REG   0x38

#define PESQI_BD_BASE_ADDR_REG  0x40

#define PESQI_BD_STAT_REG   0x44

#define PESQI_BD_POLL_CTRL_REG  0x48

#define PESQI_BD_TX_DMA_STAT_REG    0x4C

#define PESQI_BD_RX_DMA_STAT_REG    0x50

#define PESQI_THRES_REG     0x54

#define PESQI_INT_SIGEN_REG 0x58

​

/* PESQI_CONF_REG fields */

#define PESQI_MODE      0x7

#define  PESQI_MODE_BOOT    0

#define  PESQI_MODE_PIO     1

#define  PESQI_MODE_DMA     2

#define  PESQI_MODE_XIP     3

#define PESQI_MODE_SHIFT    0

#define PESQI_CPHA      BIT(3)

#define PESQI_CPOL      BIT(4)

#define PESQI_LSBF      BIT(5)

#define PESQI_RXLATCH       BIT(7)

#define PESQI_SERMODE       BIT(8)

#define PESQI_WP_EN     BIT(9)

#define PESQI_HOLD_EN       BIT(10)

#define PESQI_BURST_EN      BIT(12)

#define PESQI_CS_CTRL_HW    BIT(15)

#define PESQI_SOFT_RESET    BIT(16)

#define PESQI_LANES_SHIFT   20

#define  PESQI_SINGLE_LANE  0

#define  PESQI_DUAL_LANE    1

#define  PESQI_QUAD_LANE    2

#define PESQI_CSEN_SHIFT    24

#define PESQI_EN        BIT(23)

​

/* PESQI_CLK_CTRL_REG fields */

#define PESQI_CLK_EN        BIT(0)

#define PESQI_CLK_STABLE    BIT(1)

#define PESQI_CLKDIV_SHIFT  8

#define PESQI_CLKDIV        0xff

​

/* PESQI_INT_THR/CMD_THR_REG */

#define PESQI_TXTHR_MASK    0x1f

#define PESQI_TXTHR_SHIFT   8

#define PESQI_RXTHR_MASK    0x1f

#define PESQI_RXTHR_SHIFT   0

​

/* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */

#define PESQI_TXEMPTY       BIT(0)

#define PESQI_TXFULL        BIT(1)

#define PESQI_TXTHR     BIT(2)

#define PESQI_RXEMPTY       BIT(3)