linux-imx

// SPDX-License-Identifier: GPL-2.0-only

/*

 * Microchip PIC32 SPI controller driver.

 *

 * Purna Chandra Mandal <purna.mandal@microchip.com>

 * Copyright (c) 2016, Microchip Technology Inc.

 */

​

#include <linux/clk.h>

#include <linux/clkdev.h>

#include <linux/delay.h>

#include <linux/dmaengine.h>

#include <linux/dma-mapping.h>

#include <linux/highmem.h>

#include <linux/module.h>

#include <linux/io.h>

#include <linux/interrupt.h>

#include <linux/of.h>

#include <linux/of_irq.h>

#include <linux/of_gpio.h>

#include <linux/of_address.h>

#include <linux/platform_device.h>

#include <linux/spi/spi.h>

​

/* SPI controller registers */

struct pic32_spi_regs {

    u32 ctrl;

    u32 ctrl_clr;

    u32 ctrl_set;

    u32 ctrl_inv;

    u32 status;

    u32 status_clr;

    u32 status_set;

    u32 status_inv;

    u32 buf;

    u32 dontuse[3];

    u32 baud;

    u32 dontuse2[3];

    u32 ctrl2;

    u32 ctrl2_clr;

    u32 ctrl2_set;

    u32 ctrl2_inv;

};

​

/* Bit fields of SPI Control Register */

#define CTRL_RX_INT_SHIFT   0  /* Rx interrupt generation */

#define  RX_FIFO_EMPTY      0

#define  RX_FIFO_NOT_EMPTY  1 /* not empty */

#define  RX_FIFO_HALF_FULL  2 /* full by half or more */

#define  RX_FIFO_FULL       3 /* completely full */

​

#define CTRL_TX_INT_SHIFT   2  /* TX interrupt generation */

#define  TX_FIFO_ALL_EMPTY  0 /* completely empty */

#define  TX_FIFO_EMPTY      1 /* empty */

#define  TX_FIFO_HALF_EMPTY 2 /* empty by half or more */

#define  TX_FIFO_NOT_FULL   3 /* atleast one empty */

​

#define CTRL_MSTEN  BIT(5) /* enable master mode */

#define CTRL_CKP    BIT(6) /* active low */

#define CTRL_CKE    BIT(8) /* Tx on falling edge */

#define CTRL_SMP    BIT(9) /* Rx at middle or end of tx */

#define CTRL_BPW_MASK   0x03   /* bits per word/sample */

#define CTRL_BPW_SHIFT  10

#define  PIC32_BPW_8    0

#define  PIC32_BPW_16   1

#define  PIC32_BPW_32   2

#define CTRL_SIDL   BIT(13) /* sleep when idle */

#define CTRL_ON     BIT(15) /* enable macro */

#define CTRL_ENHBUF BIT(16) /* enable enhanced buffering */

#define CTRL_MCLKSEL    BIT(23) /* select clock source */

#define CTRL_MSSEN  BIT(28) /* macro driven /SS */

#define CTRL_FRMEN  BIT(31) /* enable framing mode */

​

/* Bit fields of SPI Status Register */

#define STAT_RF_EMPTY   BIT(5) /* RX Fifo empty */

#define STAT_RX_OV  BIT(6) /* err, s/w needs to clear */

#define STAT_TX_UR  BIT(8) /* UR in Framed SPI modes */

#define STAT_FRM_ERR    BIT(12) /* Multiple Frame Sync pulse */

#define STAT_TF_LVL_MASK    0x1F

#define STAT_TF_LVL_SHIFT   16

#define STAT_RF_LVL_MASK    0x1F

#define STAT_RF_LVL_SHIFT   24

​

/* Bit fields of SPI Baud Register */

#define BAUD_MASK       0x1ff

​

/* Bit fields of SPI Control2 Register */

#define CTRL2_TX_UR_EN      BIT(10) /* Enable int on Tx under-run */

#define CTRL2_RX_OV_EN      BIT(11) /* Enable int on Rx over-run */

#define CTRL2_FRM_ERR_EN    BIT(12) /* Enable frame err int */

​

/* Minimum DMA transfer size */