linux-imx

/*

 * PXA2xx SPI DMA engine support.

 *

 * Copyright (C) 2013, Intel Corporation

 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

​

#include <linux/device.h>

#include <linux/dma-mapping.h>

#include <linux/dmaengine.h>

#include <linux/pxa2xx_ssp.h>

#include <linux/scatterlist.h>

#include <linux/sizes.h>

#include <linux/spi/spi.h>

#include <linux/spi/pxa2xx_spi.h>

​

#include "spi-pxa2xx.h"

​

static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,

                         bool error)

{

    struct spi_message *msg = drv_data->controller->cur_msg;

​

    /*

     * It is possible that one CPU is handling ROR interrupt and other

     * just gets DMA completion. Calling pump_transfers() twice for the

     * same transfer leads to problems thus we prevent concurrent calls

     * by using ->dma_running.

     */

    if (atomic_dec_and_test(&drv_data->dma_running)) {

        /*

         * If the other CPU is still handling the ROR interrupt we

         * might not know about the error yet. So we re-check the

         * ROR bit here before we clear the status register.

         */

        if (!error) {

            u32 status = pxa2xx_spi_read(drv_data, SSSR)

                     & drv_data->mask_sr;

            error = status & SSSR_ROR;

        }

​

        /* Clear status & disable interrupts */

        pxa2xx_spi_write(drv_data, SSCR1,

                 pxa2xx_spi_read(drv_data, SSCR1)

                 & ~drv_data->dma_cr1);

        write_SSSR_CS(drv_data, drv_data->clear_sr);

        if (!pxa25x_ssp_comp(drv_data))

            pxa2xx_spi_write(drv_data, SSTO, 0);

​

        if (error) {

            /* In case we got an error we disable the SSP now */

            pxa2xx_spi_write(drv_data, SSCR0,

                     pxa2xx_spi_read(drv_data, SSCR0)

                     & ~SSCR0_SSE);

            msg->status = -EIO;

        }

​

        spi_finalize_current_transfer(drv_data->controller);

    }

}

​

static void pxa2xx_spi_dma_callback(void *data)

{

    pxa2xx_spi_dma_transfer_complete(data, false);

}

​

static struct dma_async_tx_descriptor *

pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,

               enum dma_transfer_direction dir,

               struct spi_transfer *xfer)

{

    struct chip_data *chip =

        spi_get_ctldata(drv_data->controller->cur_msg->spi);

    enum dma_slave_buswidth width;

    struct dma_slave_config cfg;

    struct dma_chan *chan;

    struct sg_table *sgt;

    int ret;

​

    switch (drv_data->n_bytes) {

    case 1:

        width = DMA_SLAVE_BUSWIDTH_1_BYTE;

        break;

    case 2:

        width = DMA_SLAVE_BUSWIDTH_2_BYTES;

        break;

    default:

        width = DMA_SLAVE_BUSWIDTH_4_BYTES;