linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * SuperH MSIOF SPI Controller Interface

 *

 * Copyright (c) 2009 Magnus Damm

 * Copyright (C) 2014 Renesas Electronics Corporation

 * Copyright (C) 2014-2017 Glider bvba

 */

​

#include <linux/bitmap.h>

#include <linux/clk.h>

#include <linux/completion.h>

#include <linux/delay.h>

#include <linux/dma-mapping.h>

#include <linux/dmaengine.h>

#include <linux/err.h>

#include <linux/gpio.h>

#include <linux/gpio/consumer.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/sh_dma.h>

​

#include <linux/spi/sh_msiof.h>

#include <linux/spi/spi.h>

​

#include <asm/unaligned.h>

​

struct sh_msiof_chipdata {

    u32 bits_per_word_mask;

    u16 tx_fifo_size;

    u16 rx_fifo_size;

    u16 ctlr_flags;

    u16 min_div_pow;

};

​

struct sh_msiof_spi_priv {

    struct spi_controller *ctlr;

    void __iomem *mapbase;

    struct clk *clk;

    struct platform_device *pdev;

    struct sh_msiof_spi_info *info;

    struct completion done;

    struct completion done_txdma;

    unsigned int tx_fifo_size;

    unsigned int rx_fifo_size;

    unsigned int min_div_pow;

    void *tx_dma_page;

    void *rx_dma_page;

    dma_addr_t tx_dma_addr;

    dma_addr_t rx_dma_addr;

    unsigned short unused_ss;

    bool native_cs_inited;

    bool native_cs_high;

    bool slave_aborted;

};

​

#define MAX_SS  3   /* Maximum number of native chip selects */

​

#define TMDR1   0x00    /* Transmit Mode Register 1 */

#define TMDR2   0x04    /* Transmit Mode Register 2 */

#define TMDR3   0x08    /* Transmit Mode Register 3 */

#define RMDR1   0x10    /* Receive Mode Register 1 */

#define RMDR2   0x14    /* Receive Mode Register 2 */

#define RMDR3   0x18    /* Receive Mode Register 3 */

#define TSCR    0x20    /* Transmit Clock Select Register */

#define RSCR    0x22    /* Receive Clock Select Register (SH, A1, APE6) */

#define CTR 0x28    /* Control Register */

#define FCTR    0x30    /* FIFO Control Register */

#define STR 0x40    /* Status Register */

#define IER 0x44    /* Interrupt Enable Register */

#define TDR1    0x48    /* Transmit Control Data Register 1 (SH, A1) */

#define TDR2    0x4c    /* Transmit Control Data Register 2 (SH, A1) */

#define TFDR    0x50    /* Transmit FIFO Data Register */

#define RDR1    0x58    /* Receive Control Data Register 1 (SH, A1) */

#define RDR2    0x5c    /* Receive Control Data Register 2 (SH, A1) */

#define RFDR    0x60    /* Receive FIFO Data Register */

​

/* TMDR1 and RMDR1 */

#define MDR1_TRMD    0x80000000 /* Transfer Mode (1 = Master mode) */

#define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */

#define MDR1_SYNCMD_SPI  0x20000000 /*   Level mode/SPI */

#define MDR1_SYNCMD_LR   0x30000000 /*   L/R mode */

#define MDR1_SYNCAC_SHIFT    25 /* Sync Polarity (1 = Active-low) */

#define MDR1_BITLSB_SHIFT    24 /* MSB/LSB First (1 = LSB first) */

#define MDR1_DTDL_SHIFT      20 /* Data Pin Bit Delay for MSIOF_SYNC */

#define MDR1_SYNCDL_SHIFT    16 /* Frame Sync Signal Timing Delay */