linux-imx

/*

 * Sonics Silicon Backplane

 * Broadcom PCI-core driver

 *

 * Copyright 2005, Broadcom Corporation

 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>

 *

 * Licensed under the GNU/GPL. See COPYING for details.

 */

​

#include "ssb_private.h"

​

#include <linux/ssb/ssb.h>

#include <linux/pci.h>

#include <linux/export.h>

#include <linux/delay.h>

#include <linux/ssb/ssb_embedded.h>

​

static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);

static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);

static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);

static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,

                u8 address, u16 data);

​

static inline

u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)

{

    return ssb_read32(pc->dev, offset);

}

​

static inline

void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)

{

    ssb_write32(pc->dev, offset, value);

}

​

static inline

u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)

{

    return ssb_read16(pc->dev, offset);

}

​

static inline

void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)

{

    ssb_write16(pc->dev, offset, value);

}

​

/**************************************************

 * Code for hostmode operation.

 **************************************************/

​

#ifdef CONFIG_SSB_PCICORE_HOSTMODE

​

#include <asm/paccess.h>

/* Probe a 32bit value on the bus and catch bus exceptions.

 * Returns nonzero on a bus exception.

 * This is MIPS specific */

#define mips_busprobe32(val, addr)  get_dbe((val), ((u32 *)(addr)))

​

/* Assume one-hot slot wiring */

#define SSB_PCI_SLOT_MAX    16

​

/* Global lock is OK, as we won't have more than one extpci anyway. */

static DEFINE_SPINLOCK(cfgspace_lock);

/* Core to access the external PCI config space. Can only have one. */

static struct ssb_pcicore *extpci_core;

​

​

static u32 get_cfgspace_addr(struct ssb_pcicore *pc,

                 unsigned int bus, unsigned int dev,

                 unsigned int func, unsigned int off)

{

    u32 addr = 0;

    u32 tmp;

​

    /* We do only have one cardbus device behind the bridge. */

    if (pc->cardbusmode && (dev > 1))

        goto out;

​

    if (bus == 0) {

        /* Type 0 transaction */

        if (unlikely(dev >= SSB_PCI_SLOT_MAX))

            goto out;

        /* Slide the window */

        tmp = SSB_PCICORE_SBTOPCI_CFG0;

        tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);

        pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);

        /* Calculate the address */

        addr = SSB_PCI_CFG;

        addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);

        addr |= (func << 8);