linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2013 Broadcom Corporation

 *

 */

​

#include <linux/debugfs.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/platform_device.h>

#include <linux/watchdog.h>

​

#define SECWDOG_CTRL_REG        0x00000000

#define SECWDOG_COUNT_REG       0x00000004

​

#define SECWDOG_RESERVED_MASK       0x1dffffff

#define SECWDOG_WD_LOAD_FLAG        0x10000000

#define SECWDOG_EN_MASK         0x08000000

#define SECWDOG_SRSTEN_MASK     0x04000000

#define SECWDOG_RES_MASK        0x00f00000

#define SECWDOG_COUNT_MASK      0x000fffff

​

#define SECWDOG_MAX_COUNT       SECWDOG_COUNT_MASK

#define SECWDOG_CLKS_SHIFT      20

#define SECWDOG_MAX_RES         15

#define SECWDOG_DEFAULT_RESOLUTION  4

#define SECWDOG_MAX_TRY         1000

​

#define SECS_TO_TICKS(x, w)     ((x) << (w)->resolution)

#define TICKS_TO_SECS(x, w)     ((x) >> (w)->resolution)

​

#define BCM_KONA_WDT_NAME       "bcm_kona_wdt"

​

struct bcm_kona_wdt {

    void __iomem *base;

    /*

     * One watchdog tick is 1/(2^resolution) seconds. Resolution can take

     * the values 0-15, meaning one tick can be 1s to 30.52us. Our default

     * resolution of 4 means one tick is 62.5ms.

     *

     * The watchdog counter is 20 bits. Depending on resolution, the maximum

     * counter value of 0xfffff expires after about 12 days (resolution 0)

     * down to only 32s (resolution 15). The default resolution of 4 gives

     * us a maximum of about 18 hours and 12 minutes before the watchdog

     * times out.

     */

    int resolution;

    spinlock_t lock;

#ifdef CONFIG_BCM_KONA_WDT_DEBUG

    unsigned long busy_count;

    struct dentry *debugfs;

#endif

};

​

static int secure_register_read(struct bcm_kona_wdt *wdt, uint32_t offset)

{

    uint32_t val;

    unsigned count = 0;

​

    /*

     * If the WD_LOAD_FLAG is set, the watchdog counter field is being

     * updated in hardware. Once the WD timer is updated in hardware, it

     * gets cleared.

     */

    do {

        if (unlikely(count > 1))

            udelay(5);

        val = readl_relaxed(wdt->base + offset);

        count++;

    } while ((val & SECWDOG_WD_LOAD_FLAG) && count < SECWDOG_MAX_TRY);

​

#ifdef CONFIG_BCM_KONA_WDT_DEBUG

    /* Remember the maximum number iterations due to WD_LOAD_FLAG */

    if (count > wdt->busy_count)

        wdt->busy_count = count;

#endif

​

    /* This is the only place we return a negative value. */

    if (val & SECWDOG_WD_LOAD_FLAG)

        return -ETIMEDOUT;

​

    /* We always mask out reserved bits. */

    val &= SECWDOG_RESERVED_MASK;

​

    return val;

}

​

#ifdef CONFIG_BCM_KONA_WDT_DEBUG

​