linux-imx

/*

 * drivers/char/watchdog/davinci_wdt.c

 *

 * Watchdog driver for DaVinci DM644x/DM646x processors

 *

 * Copyright (C) 2006-2013 Texas Instruments.

 *

 * 2007 (c) MontaVista Software, Inc. This file is licensed under

 * the terms of the GNU General Public License version 2. This program

 * is licensed "as is" without any warranty of any kind, whether express

 * or implied.

 */

​

#include <linux/module.h>

#include <linux/moduleparam.h>

#include <linux/mod_devicetable.h>

#include <linux/types.h>

#include <linux/kernel.h>

#include <linux/watchdog.h>

#include <linux/platform_device.h>

#include <linux/io.h>

#include <linux/device.h>

#include <linux/clk.h>

#include <linux/err.h>

​

#define MODULE_NAME "DAVINCI-WDT: "

​

#define DEFAULT_HEARTBEAT 60

#define MAX_HEARTBEAT     600   /* really the max margin is 264/27MHz*/

​

/* Timer register set definition */

#define PID12   (0x0)

#define EMUMGT  (0x4)

#define TIM12   (0x10)

#define TIM34   (0x14)

#define PRD12   (0x18)

#define PRD34   (0x1C)

#define TCR (0x20)

#define TGCR    (0x24)

#define WDTCR   (0x28)

​

/* TCR bit definitions */

#define ENAMODE12_DISABLED  (0 << 6)

#define ENAMODE12_ONESHOT   (1 << 6)

#define ENAMODE12_PERIODIC  (2 << 6)

​

/* TGCR bit definitions */

#define TIM12RS_UNRESET     (1 << 0)

#define TIM34RS_UNRESET     (1 << 1)

#define TIMMODE_64BIT_WDOG      (2 << 2)

​

/* WDTCR bit definitions */

#define WDEN            (1 << 14)

#define WDFLAG          (1 << 15)

#define WDKEY_SEQ0      (0xa5c6 << 16)

#define WDKEY_SEQ1      (0xda7e << 16)

​

static int heartbeat;

​

/*

 * struct to hold data for each WDT device

 * @base - base io address of WD device

 * @clk - source clock of WDT

 * @wdd - hold watchdog device as is in WDT core

 */

struct davinci_wdt_device {

    void __iomem        *base;

    struct clk      *clk;

    struct watchdog_device  wdd;

};

​

static int davinci_wdt_start(struct watchdog_device *wdd)

{

    u32 tgcr;

    u32 timer_margin;

    unsigned long wdt_freq;

    struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);

​

    wdt_freq = clk_get_rate(davinci_wdt->clk);

​

    /* disable, internal clock source */

    iowrite32(0, davinci_wdt->base + TCR);

    /* reset timer, set mode to 64-bit watchdog, and unreset */

    iowrite32(0, davinci_wdt->base + TGCR);

    tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;

    iowrite32(tgcr, davinci_wdt->base + TGCR);

    /* clear counter regs */

    iowrite32(0, davinci_wdt->base + TIM12);

    iowrite32(0, davinci_wdt->base + TIM34);

    /* set timeout period */

    timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);

    iowrite32(timer_margin, davinci_wdt->base + PRD12);