linux-imx

/*

 * Imagination Technologies PowerDown Controller Watchdog Timer.

 *

 * Copyright (c) 2014 Imagination Technologies Ltd.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published by

 * the Free Software Foundation.

 *

 * Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione

 *                                                     2012 Henrik Nordstrom

 *

 * Notes

 * -----

 * The timeout value is rounded to the next power of two clock cycles.

 * This is configured using the PDC_WDT_CONFIG register, according to this

 * formula:

 *

 *     timeout = 2^(delay + 1) clock cycles

 *

 * Where 'delay' is the value written in PDC_WDT_CONFIG register.

 *

 * Therefore, the hardware only allows to program watchdog timeouts, expressed

 * as a power of two number of watchdog clock cycles. The current implementation

 * guarantees that the actual watchdog timeout will be _at least_ the value

 * programmed in the imgpdg_wdt driver.

 *

 * The following table shows how the user-configured timeout relates

 * to the actual hardware timeout (watchdog clock @ 40000 Hz):

 *

 * input timeout | WD_DELAY | actual timeout

 * -----------------------------------

 *      10       |   18     |  13 seconds

 *      20       |   19     |  26 seconds

 *      30       |   20     |  52 seconds

 *      60       |   21     |  104 seconds

 *

 * Albeit coarse, this granularity would suffice most watchdog uses.

 * If the platform allows it, the user should be able to change the watchdog

 * clock rate and achieve a finer timeout granularity.

 */

​

#include <linux/clk.h>

#include <linux/io.h>

#include <linux/log2.h>

#include <linux/module.h>

#include <linux/mod_devicetable.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include <linux/watchdog.h>

​

/* registers */

#define PDC_WDT_SOFT_RESET      0x00

#define PDC_WDT_CONFIG          0x04

  #define PDC_WDT_CONFIG_ENABLE     BIT(31)

  #define PDC_WDT_CONFIG_DELAY_MASK 0x1f

​

#define PDC_WDT_TICKLE1         0x08

#define PDC_WDT_TICKLE1_MAGIC       0xabcd1234

#define PDC_WDT_TICKLE2         0x0c

#define PDC_WDT_TICKLE2_MAGIC       0x4321dcba

​

#define PDC_WDT_TICKLE_STATUS_MASK  0x7