linux-imx

// SPDX-License-Identifier: GPL-2.0+

/*

 * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt

 *

 * (C) Copyright 2013 - 2014 Xilinx, Inc.

 * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)

 */

​

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/module.h>

#include <linux/types.h>

#include <linux/kernel.h>

#include <linux/ioport.h>

#include <linux/watchdog.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_address.h>

​

/* Register offsets for the Wdt device */

#define XWT_TWCSR0_OFFSET   0x0 /* Control/Status Register0 */

#define XWT_TWCSR1_OFFSET   0x4 /* Control/Status Register1 */

#define XWT_TBR_OFFSET      0x8 /* Timebase Register Offset */

​

/* Control/Status Register Masks  */

#define XWT_CSR0_WRS_MASK   0x00000008 /* Reset status */

#define XWT_CSR0_WDS_MASK   0x00000004 /* Timer state  */

#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */

​

/* Control/Status Register 0/1 bits  */

#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */

​

/* SelfTest constants */

#define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000

#define XWT_TIMER_FAILED            0xFFFFFFFF

​

#define WATCHDOG_NAME     "Xilinx Watchdog"

​

struct xwdt_device {

    void __iomem *base;

    u32 wdt_interval;

    spinlock_t spinlock;

    struct watchdog_device xilinx_wdt_wdd;

    struct clk      *clk;

};

​

static int xilinx_wdt_start(struct watchdog_device *wdd)

{

    int ret;

    u32 control_status_reg;

    struct xwdt_device *xdev = watchdog_get_drvdata(wdd);

​

    ret = clk_enable(xdev->clk);

    if (ret) {

        dev_err(wdd->parent, "Failed to enable clock\n");

        return ret;

    }

​

    spin_lock(&xdev->spinlock);

​

    /* Clean previous status and enable the watchdog timer */

    control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);

    control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);

​

    iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),

          xdev->base + XWT_TWCSR0_OFFSET);

​

    iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);

​

    spin_unlock(&xdev->spinlock);

​

    return 0;

}

​

static int xilinx_wdt_stop(struct watchdog_device *wdd)

{

    u32 control_status_reg;

    struct xwdt_device *xdev = watchdog_get_drvdata(wdd);

​

    spin_lock(&xdev->spinlock);

​

    control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);

​

    iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),

          xdev->base + XWT_TWCSR0_OFFSET);

​

    iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);

​

    spin_unlock(&xdev->spinlock);

​

    clk_disable(xdev->clk);