linux-imx

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.

 */

​

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/watchdog.h>

​

/* minimum and maximum watchdog trigger timeout, in seconds */

#define MIN_WDT_TIMEOUT         1

#define MAX_WDT_TIMEOUT         255

​

/*

 * Base of the WDT registers, from the timer base address.  There are

 * actually 5 watchdogs that can be configured (by pairing with an available

 * timer), at bases 0x100 + (WDT ID) * 0x20, where WDT ID is 0 through 4.

 * This driver only configures the first watchdog (WDT ID 0).

 */

#define WDT_BASE            0x100

#define WDT_ID              0

​

/*

 * Register base of the timer that's selected for pairing with the watchdog.

 * This driver arbitrarily uses timer 5, which is currently unused by

 * other drivers (in particular, the Tegra clocksource driver).  If this

 * needs to change, take care that the new timer is not used by the

 * clocksource driver.

 */

#define WDT_TIMER_BASE          0x60

#define WDT_TIMER_ID            5

​

/* WDT registers */

#define WDT_CFG             0x0

#define WDT_CFG_PERIOD_SHIFT        4

#define WDT_CFG_PERIOD_MASK     0xff

#define WDT_CFG_INT_EN          (1 << 12)

#define WDT_CFG_PMC2CAR_RST_EN      (1 << 15)

#define WDT_STS             0x4

#define WDT_STS_COUNT_SHIFT     4

#define WDT_STS_COUNT_MASK      0xff

#define WDT_STS_EXP_SHIFT       12

#define WDT_STS_EXP_MASK        0x3

#define WDT_CMD             0x8

#define WDT_CMD_START_COUNTER       (1 << 0)

#define WDT_CMD_DISABLE_COUNTER     (1 << 1)

#define WDT_UNLOCK          (0xc)

#define WDT_UNLOCK_PATTERN      (0xc45a << 0)

​

/* Timer registers */

#define TIMER_PTV           0x0

#define TIMER_EN            (1 << 31)

#define TIMER_PERIODIC          (1 << 30)

​

struct tegra_wdt {

    struct watchdog_device  wdd;

    void __iomem        *wdt_regs;

    void __iomem        *tmr_regs;

};