Commits
Andrew Jiang committed 58bb0e63dd9
drm/amd/display: Correct timings in build scaling params A previous patch set the addressable timing as active + border, when in fact, the VESA standard specifies active as equal to addressable + border. This patch makes the fix more correct and in line with the standard. Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>