Source
274
274
u32 accuracy = 0;
275
275
276
276
clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
277
277
if (!clk_data)
278
278
return;
279
279
clk_data->num = MAX_CLKS;
280
280
hws = clk_data->hws;
281
281
282
282
base = of_io_request_and_map(np, 0, np->name);
283
283
if (IS_ERR(base))
284
-
panic("%s: unable to map resource", np->name);
284
+
panic("%pOFn: unable to map resource", np);
285
285
286
286
/* register pll */
287
287
rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;
288
288
289
289
ref_clk = of_clk_get_parent_name(np, 0);
290
290
accuracy = clk_get_accuracy(__clk_lookup(ref_clk));
291
291
hw = clk_hw_register_fixed_rate_with_accuracy(NULL, pll_clk,
292
292
ref_clk, 0, rate, accuracy);
293
293
294
294
if (IS_ERR(hw))
295
-
panic("%s: can't register REFCLK. Check DT!", np->name);
295
+
panic("%pOFn: can't register REFCLK. Check DT!", np);
296
296
297
297
for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {
298
298
const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];
299
299
300
300
mc->parent_names[0] = ref_clk;
301
301
mc->parent_names[1] = pll_clk;
302
302
hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names,
303
303
mc->num_parents, mc->flags, base + mc->offset,
304
304
0, mc->mask, 0, mc->table, &asm9260_clk_lock);
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305
}