Source of dma-jz4740.c - linux-imx - PHYTEC BitBucket (Stash)

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    enum dma_transfer_direction direction;
    bool cyclic;
​
    unsigned int num_sgs;
    struct jz4740_dma_sg sg[];
};
​
struct jz4740_dmaengine_chan {
    struct virt_dma_chan vchan;
    unsigned int id;
    struct dma_slave_config config;
​
    dma_addr_t fifo_addr;
    unsigned int transfer_shift;
​
    struct jz4740_dma_desc *desc;
    unsigned int next_sg;
};
​
struct jz4740_dma_dev {
    struct dma_device ddev;
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    else if (maxburst <= 3)
        return JZ4740_DMA_TRANSFER_SIZE_2BYTE;
    else if (maxburst <= 15)
        return JZ4740_DMA_TRANSFER_SIZE_4BYTE;
    else if (maxburst <= 31)
        return JZ4740_DMA_TRANSFER_SIZE_16BYTE;
​
    return JZ4740_DMA_TRANSFER_SIZE_32BYTE;
}
​
static int jz4740_dma_slave_config(struct dma_chan *c,
                   struct dma_slave_config *config)
static int jz4740_dma_slave_config_write(struct dma_chan *c,
                   struct dma_slave_config *config,
                   enum dma_transfer_direction direction)
{
    struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
    struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
    enum jz4740_dma_width src_width;
    enum jz4740_dma_width dst_width;
    enum jz4740_dma_transfer_size transfer_size;
    enum jz4740_dma_flags flags;
    uint32_t cmd;
​
    switch (config->direction) {
    switch (direction) {
    case DMA_MEM_TO_DEV:
        flags = JZ4740_DMA_SRC_AUTOINC;
        transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
        chan->fifo_addr = config->dst_addr;
        break;
    case DMA_DEV_TO_MEM:
        flags = JZ4740_DMA_DST_AUTOINC;
        transfer_size = jz4740_dma_maxburst(config->src_maxburst);
        chan->fifo_addr = config->src_addr;
        break;
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    cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
​
    jz4740_dma_write(dmadev, JZ_REG_DMA_CMD(chan->id), cmd);
    jz4740_dma_write(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0);
    jz4740_dma_write(dmadev, JZ_REG_DMA_REQ_TYPE(chan->id),
        config->slave_id);
​
    return 0;
}
​
static int jz4740_dma_slave_config(struct dma_chan *c,
                   struct dma_slave_config *config)
{
    struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
​
    memcpy(&chan->config, config, sizeof(*config));
    return 0;
}
​
static int jz4740_dma_terminate_all(struct dma_chan *c)
{
    struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
    struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
    unsigned long flags;
    LIST_HEAD(head);
​
    spin_lock_irqsave(&chan->vchan.lock, flags);
    jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
            JZ_DMA_STATUS_CTRL_ENABLE);
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​
    for_each_sg(sgl, sg, sg_len, i) {
        desc->sg[i].addr = sg_dma_address(sg);
        desc->sg[i].len = sg_dma_len(sg);
    }
​
    desc->num_sgs = sg_len;
    desc->direction = direction;
    desc->cyclic = false;
​
    jz4740_dma_slave_config_write(c, &chan->config, direction);
​
    return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
}
​
static struct dma_async_tx_descriptor *jz4740_dma_prep_dma_cyclic(
    struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
    size_t period_len, enum dma_transfer_direction direction,
    unsigned long flags)
{
    struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
    struct jz4740_dma_desc *desc;
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    for (i = 0; i < num_periods; i++) {
        desc->sg[i].addr = buf_addr;
        desc->sg[i].len = period_len;
        buf_addr += period_len;
    }
​
    desc->num_sgs = num_periods;
    desc->direction = direction;
    desc->cyclic = true;
​
    jz4740_dma_slave_config_write(c, &chan->config, direction);
​
    return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
}
​
static size_t jz4740_dma_desc_residue(struct jz4740_dmaengine_chan *chan,
    struct jz4740_dma_desc *desc, unsigned int next_sg)
{
    struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
    unsigned int residue, count;
    unsigned int i;
​