Source
114
114
}
115
115
116
116
err = clk_prepare_enable(priv->clk);
117
117
if (err) {
118
118
dev_err(&pdev->dev, "unable to enable clock\n");
119
119
return err;
120
120
}
121
121
122
122
clk_disable(priv->clk);
123
123
124
-
br = fpga_bridge_create(&pdev->dev, "Xilinx PR Decoupler",
125
-
&xlnx_pr_decoupler_br_ops, priv);
124
+
br = devm_fpga_bridge_create(&pdev->dev, "Xilinx PR Decoupler",
125
+
&xlnx_pr_decoupler_br_ops, priv);
126
126
if (!br) {
127
127
err = -ENOMEM;
128
128
goto err_clk;
129
129
}
130
130
131
131
platform_set_drvdata(pdev, br);
132
132
133
133
err = fpga_bridge_register(br);
134
134
if (err) {
135
135
dev_err(&pdev->dev, "unable to register Xilinx PR Decoupler");