Source of gpio-max77620.c - linux-imx - PHYTEC BitBucket (Stash)

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#define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
​
struct max77620_gpio {
    struct gpio_chip    gpio_chip;
    struct regmap       *rmap;
    struct device       *dev;
};
​
static const struct regmap_irq max77620_gpio_irqs[] = {
    [0] = {
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
        .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
        .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
        .reg_offset = 0,
        .type_reg_offset = 0,
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
        .type = {
            .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
            .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
            .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
            .type_reg_offset = 0,
            .types_supported = IRQ_TYPE_EDGE_BOTH,
        },
    },
    [1] = {
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
        .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
        .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
        .reg_offset = 0,
        .type_reg_offset = 1,
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
        .type = {
            .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
            .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
            .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
            .type_reg_offset = 1,
            .types_supported = IRQ_TYPE_EDGE_BOTH,
        },
    },
    [2] = {
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
        .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
        .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
        .reg_offset = 0,
        .type_reg_offset = 2,
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
        .type = {
            .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
            .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
            .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
            .type_reg_offset = 2,
            .types_supported = IRQ_TYPE_EDGE_BOTH,
        },
    },
    [3] = {
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
        .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
        .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
        .reg_offset = 0,
        .type_reg_offset = 3,
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
        .type = {
            .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
            .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
            .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
            .type_reg_offset = 3,
            .types_supported = IRQ_TYPE_EDGE_BOTH,
        },
    },
    [4] = {
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
        .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
        .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
        .reg_offset = 0,
        .type_reg_offset = 4,
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
        .type = {
            .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
            .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
            .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
            .type_reg_offset = 4,
            .types_supported = IRQ_TYPE_EDGE_BOTH,
        },
    },
    [5] = {
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
        .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
        .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
        .reg_offset = 0,
        .type_reg_offset = 5,
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
        .type = {
            .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
            .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
            .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
            .type_reg_offset = 5,
            .types_supported = IRQ_TYPE_EDGE_BOTH,
        },
    },
    [6] = {
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
        .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
        .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
        .reg_offset = 0,
        .type_reg_offset = 6,
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
        .type = {
            .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
            .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
            .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
            .type_reg_offset = 6,
            .types_supported = IRQ_TYPE_EDGE_BOTH,
        },
    },
    [7] = {
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
        .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
        .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
        .reg_offset = 0,
        .type_reg_offset = 7,
        .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
        .type = {
            .type_rising_val = MAX77620_CNFG_GPIO_INT_RISING,
            .type_falling_val = MAX77620_CNFG_GPIO_INT_FALLING,
            .type_reg_mask = MAX77620_CNFG_GPIO_INT_MASK,
            .type_reg_offset = 7,
            .types_supported = IRQ_TYPE_EDGE_BOTH,
        },
    },
};
​
static const struct regmap_irq_chip max77620_gpio_irq_chip = {
    .name = "max77620-gpio",
    .irqs = max77620_gpio_irqs,
    .num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
    .num_regs = 1,
    .num_type_reg = 8,
    .irq_reg_stride = 1,