Source of gpio-mt7621.c - linux-imx - PHYTEC BitBucket (Stash)

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#define GPIO_REG_DSET       0x30
#define GPIO_REG_DCLR       0x40
#define GPIO_REG_REDGE      0x50
#define GPIO_REG_FEDGE      0x60
#define GPIO_REG_HLVL       0x70
#define GPIO_REG_LLVL       0x80
#define GPIO_REG_STAT       0x90
#define GPIO_REG_EDGE       0xA0
​
struct mtk_gc {
    struct irq_chip irq_chip;
    struct gpio_chip chip;
    spinlock_t lock;
    int bank;
    u32 rising;
    u32 falling;
    u32 hlevel;
    u32 llevel;
};
​
/**
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        rg->hlevel |= mask;
        break;
    case IRQ_TYPE_LEVEL_LOW:
        rg->llevel |= mask;
        break;
    }
​
    return 0;
}
​
static struct irq_chip mediatek_gpio_irq_chip = {
    .irq_unmask     = mediatek_gpio_irq_unmask,
    .irq_mask       = mediatek_gpio_irq_mask,
    .irq_mask_ack       = mediatek_gpio_irq_mask,
    .irq_set_type       = mediatek_gpio_irq_type,
};
​
static int
mediatek_gpio_xlate(struct gpio_chip *chip,
            const struct of_phandle_args *spec, u32 *flags)
{
    int gpio = spec->args[0];
    struct mtk_gc *rg = to_mediatek_gpio(chip);
​
    if (rg->bank != gpio / MTK_BANK_WIDTH)
        return -EINVAL;
​
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    if (!rg->chip.label)
        return -ENOMEM;
​
    ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
    if (ret < 0) {
        dev_err(dev, "Could not register gpio %d, ret=%d\n",
            rg->chip.ngpio, ret);
        return ret;
    }
​
    rg->irq_chip.name = dev_name(dev);
    rg->irq_chip.parent_device = dev;
    rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
    rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
    rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;
    rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;
​
    if (mtk->gpio_irq) {
        /*
         * Manually request the irq here instead of passing
         * a flow-handler to gpiochip_set_chained_irqchip,
         * because the irq is shared.
         */
        ret = devm_request_irq(dev, mtk->gpio_irq,
                       mediatek_gpio_irq_handler, IRQF_SHARED,
                       rg->chip.label, &rg->chip);
​
        if (ret) {
            dev_err(dev, "Error requesting IRQ %d: %d\n",
                mtk->gpio_irq, ret);
            return ret;
        }
​
        ret = gpiochip_irqchip_add(&rg->chip, &mediatek_gpio_irq_chip,
        ret = gpiochip_irqchip_add(&rg->chip, &rg->irq_chip,
                       0, handle_simple_irq, IRQ_TYPE_NONE);
        if (ret) {
            dev_err(dev, "failed to add gpiochip_irqchip\n");
            return ret;
        }
​
        gpiochip_set_chained_irqchip(&rg->chip, &mediatek_gpio_irq_chip,
        gpiochip_set_chained_irqchip(&rg->chip, &rg->irq_chip,
                         mtk->gpio_irq, NULL);
    }
​
    /* set polarity to low for all gpios */
    mtk_gpio_w32(rg, GPIO_REG_POL, 0);
​
    dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);
​
    return 0;
}
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    if (!mtk)
        return -ENOMEM;
​
    mtk->base = devm_ioremap_resource(dev, res);
    if (IS_ERR(mtk->base))
        return PTR_ERR(mtk->base);
​
    mtk->gpio_irq = irq_of_parse_and_map(np, 0);
    mtk->dev = dev;
    platform_set_drvdata(pdev, mtk);
    mediatek_gpio_irq_chip.name = dev_name(dev);
​
    for (i = 0; i < MTK_BANK_CNT; i++) {
        ret = mediatek_gpio_bank_probe(dev, np, i);
        if (ret)
            return ret;
    }
​
    return 0;
}
​