Source
320
320
.dma_host_set = ide_dma_host_set,
321
321
.dma_setup = ide_dma_setup,
322
322
.dma_start = ide_dma_start,
323
323
.dma_end = cmd646_1_dma_end,
324
324
.dma_test_irq = ide_dma_test_irq,
325
325
.dma_lost_irq = ide_dma_lost_irq,
326
326
.dma_timer_expiry = ide_dma_sff_timer_expiry,
327
327
.dma_sff_read_status = ide_dma_sff_read_status,
328
328
};
329
329
330
-
static const struct ide_port_info cmd64x_chipsets[] __devinitconst = {
330
+
static const struct ide_port_info cmd64x_chipsets[] = {
331
331
{ /* 0: CMD643 */
332
332
.name = DRV_NAME,
333
333
.init_chipset = init_chipset_cmd64x,
334
334
.enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
335
335
.port_ops = &cmd64x_port_ops,
336
336
.host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
337
337
IDE_HFLAG_ABUSE_PREFETCH |
338
338
IDE_HFLAG_SERIALIZE,
339
339
.pio_mask = ATA_PIO5,
340
340
.mwdma_mask = ATA_MWDMA2,
366
366
.init_chipset = init_chipset_cmd64x,
367
367
.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
368
368
.port_ops = &cmd648_port_ops,
369
369
.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
370
370
.pio_mask = ATA_PIO5,
371
371
.mwdma_mask = ATA_MWDMA2,
372
372
.udma_mask = ATA_UDMA5,
373
373
}
374
374
};
375
375
376
-
static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
376
+
static int cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
377
377
{
378
378
struct ide_port_info d;
379
379
u8 idx = id->driver_data;
380
380
381
381
d = cmd64x_chipsets[idx];
382
382
383
383
if (idx == 1) {
384
384
/*
385
385
* UltraDMA only supported on PCI646U and PCI646U2, which
386
386
* correspond to revisions 0x03, 0x05 and 0x07 respectively.