linux-imx

​

    raw_spin_lock(&irq_controller_lock);

    reg = hip04_dist_base(d) + GIC_DIST_TARGET + ((hip04_irq(d) * 2) & ~3);

    mask = 0xffff << shift;

    bit = hip04_cpu_map[cpu] << shift;

    val = readl_relaxed(reg) & ~mask;

    writel_relaxed(val | bit, reg);

    raw_spin_unlock(&irq_controller_lock);

​

    return IRQ_SET_MASK_OK;

}

#endif

​

static void __exception_irq_entry hip04_handle_irq(struct pt_regs *regs)

{

    u32 irqstat, irqnr;

    void __iomem *cpu_base = hip04_data.cpu_base;

​

    do {

    if (hw < 32) {

        irq_set_percpu_devid(irq);

        irq_set_chip_and_handler(irq, &hip04_irq_chip,

                     handle_percpu_devid_irq);

        irq_set_status_flags(irq, IRQ_NOAUTOEN);

    } else {

        irq_set_chip_and_handler(irq, &hip04_irq_chip,

                     handle_fasteoi_irq);

        irq_set_probe(irq);

    }

    irq_set_chip_data(irq, d->host_data);

    return 0;

}

​

static int hip04_irq_domain_xlate(struct irq_domain *d,

                  struct device_node *controller,

                  const u32 *intspec, unsigned int intsize,

                  unsigned long *out_hwirq,

                  unsigned int *out_type)