Source
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.reg_defaults = twl6040_defaults,
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.num_reg_defaults = ARRAY_SIZE(twl6040_defaults),
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.max_register = TWL6040_REG_STATUS, /* 0x2e */
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.readable_reg = twl6040_readable_reg,
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.volatile_reg = twl6040_volatile_reg,
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.writeable_reg = twl6040_writeable_reg,
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.cache_type = REGCACHE_RBTREE,
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-
.use_single_rw = true,
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+
.use_single_read = true,
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+
.use_single_write = true,
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};
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static const struct regmap_irq twl6040_irqs[] = {
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{ .reg_offset = 0, .mask = TWL6040_THINT, },
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{ .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, },
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623
{ .reg_offset = 0, .mask = TWL6040_HOOKINT, },
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{ .reg_offset = 0, .mask = TWL6040_HFINT, },
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{ .reg_offset = 0, .mask = TWL6040_VIBINT, },
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{ .reg_offset = 0, .mask = TWL6040_READYINT, },
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};