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// SPDX-License-Identifier: GPL-2.02
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/*3
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* STM32 Factory-programmed memory read access driver4
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*5
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved6
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com> for STMicroelectronics.7
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*/8
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#include <linux/arm-smccc.h>9
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#include <linux/io.h>10
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#include <linux/module.h>11
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#include <linux/nvmem-provider.h>12
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#include <linux/of_device.h>13
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/* BSEC secure service access from non-secure */16
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#define STM32_SMC_BSEC 0x8200100317
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#define STM32_SMC_READ_SHADOW 0x0118
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#define STM32_SMC_PROG_OTP 0x0219
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#define STM32_SMC_WRITE_SHADOW 0x0320
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#define STM32_SMC_READ_OTP 0x0421
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/* shadow registers offest */23
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#define STM32MP15_BSEC_DATA0 0x20024
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/* 32 (x 32-bits) lower shadow registers */26
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#define STM32MP15_BSEC_NUM_LOWER 3227
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struct stm32_romem_cfg {29
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int size;30
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};31
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struct stm32_romem_priv {15
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void __iomem *base;16
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struct nvmem_config cfg;17
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};18
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static int stm32_romem_read(void *context, unsigned int offset, void *buf,20
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size_t bytes)21
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{22
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struct stm32_romem_priv *priv = context;23
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u8 *buf8 = buf;24
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int i;25
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for (i = offset; i < offset + bytes; i++)27
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*buf8++ = readb_relaxed(priv->base + i);28
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return 0;30
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}31
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static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result)51
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{52
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#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)53
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struct arm_smccc_res res;54
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arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res);56
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if (res.a0)57
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return -EIO;58
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if (result)60
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*result = (u32)res.a1;61
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return 0;63
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#else64
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return -ENXIO;65
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#endif66
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}67
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static int stm32_bsec_read(void *context, unsigned int offset, void *buf,69
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size_t bytes)70
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{71
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struct stm32_romem_priv *priv = context;72
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struct device *dev = priv->cfg.dev;73
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u32 roffset, rbytes, val;74
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u8 *buf8 = buf, *val8 = (u8 *)&val;75
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int i, j = 0, ret, skip_bytes, size;76
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/* Round unaligned access to 32-bits */78
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roffset = rounddown(offset, 4);79
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skip_bytes = offset & 0x3;80
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rbytes = roundup(bytes + skip_bytes, 4);81
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if (roffset + rbytes > priv->cfg.size)83
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return -EINVAL;84
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for (i = roffset; (i < roffset + rbytes); i += 4) {86
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u32 otp = i >> 2;87
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if (otp < STM32MP15_BSEC_NUM_LOWER) {89
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/* read lower data from shadow registers */90
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val = readl_relaxed(91
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priv->base + STM32MP15_BSEC_DATA0 + i);92
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} else {93
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ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0,94
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&val);95
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if (ret) {96
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dev_err(dev, "Can't read data%d (%d)\n", otp,97
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ret);98
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return ret;99
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}100
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}101
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/* skip first bytes in case of unaligned read */102
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if (skip_bytes)103
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size = min(bytes, (size_t)(4 - skip_bytes));104
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else105
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size = min(bytes, (size_t)4);106
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memcpy(&buf8[j], &val8[skip_bytes], size);107
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bytes -= size;108
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j += size;109
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skip_bytes = 0;110
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}111
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return 0;113
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}114
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static int stm32_bsec_write(void *context, unsigned int offset, void *buf,116
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size_t bytes)117
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{118
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struct stm32_romem_priv *priv = context;119
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struct device *dev = priv->cfg.dev;120
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u32 *buf32 = buf;121
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int ret, i;122
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/* Allow only writing complete 32-bits aligned words */124
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if ((bytes % 4) || (offset % 4))125
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return -EINVAL;126
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for (i = offset; i < offset + bytes; i += 4) {128
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ret = stm32_bsec_smc(STM32_SMC_PROG_OTP, i >> 2, *buf32++,129
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NULL);130
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if (ret) {131
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dev_err(dev, "Can't write data%d (%d)\n", i >> 2, ret);132
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return ret;133
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}134
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}135
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return 0;137
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}138
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static int stm32_romem_probe(struct platform_device *pdev)33
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{141
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const struct stm32_romem_cfg *cfg;34
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struct device *dev = &pdev->dev;35
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struct stm32_romem_priv *priv;36
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struct resource *res;37
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);39
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if (!priv)40
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return -ENOMEM;41
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);43
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priv->base = devm_ioremap_resource(dev, res);44
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if (IS_ERR(priv->base))45
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return PTR_ERR(priv->base);46
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priv->cfg.name = "stm32-romem";48
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priv->cfg.read_only = true;49
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priv->cfg.word_size = 1;50
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priv->cfg.stride = 1;51
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priv->cfg.size = resource_size(res);52
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priv->cfg.reg_read = stm32_romem_read;53
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priv->cfg.dev = dev;54
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priv->cfg.priv = priv;55
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priv->cfg.owner = THIS_MODULE;56
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cfg = (const struct stm32_romem_cfg *)163
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of_match_device(dev->driver->of_match_table, dev)->data;164
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if (!cfg) {165
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priv->cfg.read_only = true;166
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priv->cfg.size = resource_size(res);167
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priv->cfg.reg_read = stm32_romem_read;168
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} else {169
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priv->cfg.size = cfg->size;170
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priv->cfg.reg_read = stm32_bsec_read;171
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priv->cfg.reg_write = stm32_bsec_write;172
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}173
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return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));58
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}59
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static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {178
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.size = 384, /* 96 x 32-bits data words */179
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};180
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static const struct of_device_id stm32_romem_of_match[] = {61
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{ .compatible = "st,stm32f4-otp", },62
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{},182
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{ .compatible = "st,stm32f4-otp", }, {183
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.compatible = "st,stm32mp15-bsec",184
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.data = (void *)&stm32mp15_bsec_cfg,185
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}, {186
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},63
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};64
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MODULE_DEVICE_TABLE(of, stm32_romem_of_match);65
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static struct platform_driver stm32_romem_driver = {67
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.probe = stm32_romem_probe,68
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.driver = {69
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.name = "stm32-romem",70
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.of_match_table = of_match_ptr(stm32_romem_of_match),71
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},72
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};