Source
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unsigned long long c;
unsigned long period_cycles;
unsigned long duty_cycles;
unsigned long term;
int ret = 0;
/*
* The clock needs to be enabled to access the PWM registers.
* Configuration can be changed at any time.
*/
if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
if (!pwm_is_enabled(pwm)) {
ret = clk_enable(ep93xx_pwm->clk);
if (ret)
return ret;
}
c = clk_get_rate(ep93xx_pwm->clk);
c *= period_ns;
do_div(c, 1000000000);
period_cycles = c;
writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
} else {
writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
}
} else {
ret = -EINVAL;
}
if (!test_bit(PWMF_ENABLED, &pwm->flags))
if (!pwm_is_enabled(pwm))
clk_disable(ep93xx_pwm->clk);
return ret;
}
static int ep93xx_pwm_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
enum pwm_polarity polarity)
{
struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
int ret;