linux-imx

    u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET

            | CR0_BHT_8BIT << CR0_BHT_OFFSET

            | CR0_SSD_ONE  << CR0_SSD_OFFSET

            | CR0_EM_BIG   << CR0_EM_OFFSET;

    u32 cr1;

    u32 dmacr = 0;

​

    cr0 |= rs->rsd << CR0_RSD_OFFSET;

    cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;

​

    if (xfer->rx_buf && xfer->tx_buf)

        cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;

    else if (xfer->rx_buf)

        cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;

    else if (use_dma)

        cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;

​

    switch (xfer->bits_per_word) {

    case 4:

        ret = -EINVAL;

        goto err_disable_spiclk;

    }

​

    pm_runtime_set_active(&pdev->dev);

    pm_runtime_enable(&pdev->dev);

​

    master->auto_runtime_pm = true;

    master->bus_num = pdev->id;

    master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;

    master->dev.of_node = pdev->dev.of_node;

    master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);

    master->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;

    master->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);

​

    master->set_cs = rockchip_spi_set_cs;

    master->transfer_one = rockchip_spi_transfer_one;

    master->max_transfer_size = rockchip_spi_max_transfer_size;

    master->handle_err = rockchip_spi_handle_err;