Source of spi-rspi.c - linux-imx - PHYTEC BitBucket (Stash)

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#define SPBFCR_TXTRG_1B     0x00    /* 31 bytes (1 byte available) */
#define SPBFCR_TXTRG_32B    0x30    /* 0 byte (32 bytes available) */
#define SPBFCR_RXTRG_1B     0x00    /* 1 byte (31 bytes available) */
#define SPBFCR_RXTRG_32B    0x07    /* 32 bytes (0 byte available) */
​
#define QSPI_BUFFER_SIZE        32u
​
struct rspi_data {
    void __iomem *addr;
    u32 max_speed_hz;
    struct spi_master *master;
    struct spi_controller *ctlr;
    wait_queue_head_t wait;
    struct clk *clk;
    u16 spcmd;
    u8 spsr;
    u8 sppcr;
    int rx_irq, tx_irq;
    const struct spi_ops *ops;
​
    unsigned dma_callbacked:1;
    unsigned byte_access:1;
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{
    if (rspi->byte_access)
        return rspi_read8(rspi, RSPI_SPDR);
    else /* 16 bit */
        return rspi_read16(rspi, RSPI_SPDR);
}
​
/* optional functions */
struct spi_ops {
    int (*set_config_register)(struct rspi_data *rspi, int access_size);
    int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
                struct spi_transfer *xfer);
    int (*transfer_one)(struct spi_controller *ctlr,
                struct spi_device *spi, struct spi_transfer *xfer);
    u16 mode_bits;
    u16 flags;
    u16 fifo_size;
};
​
/*
 * functions for RSPI on legacy SH
 */
static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
{
Show more
​
static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
{
    return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
}
​
static int rspi_data_out(struct rspi_data *rspi, u8 data)
{
    int error = rspi_wait_for_tx_empty(rspi);
    if (error < 0) {
        dev_err(&rspi->master->dev, "transmit timeout\n");
        dev_err(&rspi->ctlr->dev, "transmit timeout\n");
        return error;
    }
    rspi_write_data(rspi, data);
    return 0;
}
​
static int rspi_data_in(struct rspi_data *rspi)
{
    int error;
    u8 data;
​
    error = rspi_wait_for_rx_full(rspi);
    if (error < 0) {
        dev_err(&rspi->master->dev, "receive timeout\n");
        dev_err(&rspi->ctlr->dev, "receive timeout\n");
        return error;
    }
    data = rspi_read_data(rspi);
    return data;
}
​
static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
                 unsigned int n)
{
    while (n-- > 0) {
Show more
                 struct sg_table *rx)
{
    struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
    u8 irq_mask = 0;
    unsigned int other_irq = 0;
    dma_cookie_t cookie;
    int ret;
​
    /* First prepare and submit the DMA request(s), as this may fail */
    if (rx) {
        desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
                    rx->sgl, rx->nents, DMA_DEV_TO_MEM,
        desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
                    rx->nents, DMA_DEV_TO_MEM,
                    DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
        if (!desc_rx) {
            ret = -EAGAIN;
            goto no_dma_rx;
        }
​
        desc_rx->callback = rspi_dma_complete;
        desc_rx->callback_param = rspi;
        cookie = dmaengine_submit(desc_rx);
        if (dma_submit_error(cookie)) {
            ret = cookie;
            goto no_dma_rx;
        }
​
        irq_mask |= SPCR_SPRIE;
    }
​
    if (tx) {
        desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
                    tx->sgl, tx->nents, DMA_MEM_TO_DEV,
        desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
                    tx->nents, DMA_MEM_TO_DEV,
                    DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
        if (!desc_tx) {
            ret = -EAGAIN;
            goto no_dma_tx;
        }
​
        if (rx) {
            /* No callback */
            desc_tx->callback = NULL;
        } else {
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    if (tx)
        disable_irq(other_irq = rspi->tx_irq);
    if (rx && rspi->rx_irq != other_irq)
        disable_irq(rspi->rx_irq);
​
    rspi_enable_irq(rspi, irq_mask);
    rspi->dma_callbacked = 0;
​
    /* Now start DMA */
    if (rx)
        dma_async_issue_pending(rspi->master->dma_rx);
        dma_async_issue_pending(rspi->ctlr->dma_rx);
    if (tx)
        dma_async_issue_pending(rspi->master->dma_tx);
        dma_async_issue_pending(rspi->ctlr->dma_tx);
​
    ret = wait_event_interruptible_timeout(rspi->wait,
                           rspi->dma_callbacked, HZ);
    if (ret > 0 && rspi->dma_callbacked) {
        ret = 0;
    } else {
        if (!ret) {
            dev_err(&rspi->master->dev, "DMA timeout\n");
            dev_err(&rspi->ctlr->dev, "DMA timeout\n");
            ret = -ETIMEDOUT;
        }
        if (tx)
            dmaengine_terminate_all(rspi->master->dma_tx);
            dmaengine_terminate_all(rspi->ctlr->dma_tx);
        if (rx)
            dmaengine_terminate_all(rspi->master->dma_rx);
            dmaengine_terminate_all(rspi->ctlr->dma_rx);
    }
​
    rspi_disable_irq(rspi, irq_mask);
​
    if (tx)
        enable_irq(rspi->tx_irq);
    if (rx && rspi->rx_irq != other_irq)
        enable_irq(rspi->rx_irq);
​
    return ret;
​
no_dma_tx:
    if (rx)
        dmaengine_terminate_all(rspi->master->dma_rx);
        dmaengine_terminate_all(rspi->ctlr->dma_rx);
no_dma_rx:
    if (ret == -EAGAIN) {
        pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
                 dev_driver_string(&rspi->master->dev),
                 dev_name(&rspi->master->dev));
                 dev_driver_string(&rspi->ctlr->dev),
                 dev_name(&rspi->ctlr->dev));
    }
    return ret;
}
​
static void rspi_receive_init(const struct rspi_data *rspi)
{
    u8 spsr;
​
    spsr = rspi_read8(rspi, RSPI_SPSR);
    if (spsr & SPSR_SPRF)
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    rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
    rspi_write8(rspi, 0, QSPI_SPBFCR);
}
​
static bool __rspi_can_dma(const struct rspi_data *rspi,
               const struct spi_transfer *xfer)
{
    return xfer->len > rspi->ops->fifo_size;
}
​
static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
             struct spi_transfer *xfer)
{
    struct rspi_data *rspi = spi_master_get_devdata(master);
    struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
​
    return __rspi_can_dma(rspi, xfer);
}
​
static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
                     struct spi_transfer *xfer)
{
    if (!rspi->master->can_dma || !__rspi_can_dma(rspi, xfer))
    if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
        return -EAGAIN;
​
    /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
    return rspi_dma_transfer(rspi, &xfer->tx_sg,
                xfer->rx_buf ? &xfer->rx_sg : NULL);
}
​
static int rspi_common_transfer(struct rspi_data *rspi,
                struct spi_transfer *xfer)
{
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    ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
    if (ret < 0)
        return ret;
​
    /* Wait for the last transmission */
    rspi_wait_for_tx_empty(rspi);
​
    return 0;
}
​
static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
                 struct spi_transfer *xfer)
static int rspi_transfer_one(struct spi_controller *ctlr,
                 struct spi_device *spi, struct spi_transfer *xfer)
{
    struct rspi_data *rspi = spi_master_get_devdata(master);
    struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
    u8 spcr;
​
    spcr = rspi_read8(rspi, RSPI_SPCR);
    if (xfer->rx_buf) {
        rspi_receive_init(rspi);
        spcr &= ~SPCR_TXMD;
    } else {
        spcr |= SPCR_TXMD;
    }
    rspi_write8(rspi, spcr, RSPI_SPCR);
​
    return rspi_common_transfer(rspi, xfer);
}
​
static int rspi_rz_transfer_one(struct spi_master *master,
static int rspi_rz_transfer_one(struct spi_controller *ctlr,
                struct spi_device *spi,
                struct spi_transfer *xfer)
{
    struct rspi_data *rspi = spi_master_get_devdata(master);
    struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
​
    rspi_rz_receive_init(rspi);
​
    return rspi_common_transfer(rspi, xfer);
}
​
static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
                    u8 *rx, unsigned int len)
{
    unsigned int i, n;
    int ret;
​
    while (len > 0) {
        n = qspi_set_send_trigger(rspi, len);
        qspi_set_receive_trigger(rspi, len);
        if (n == QSPI_BUFFER_SIZE) {
            ret = rspi_wait_for_tx_empty(rspi);
            if (ret < 0) {
                dev_err(&rspi->master->dev, "transmit timeout\n");
                dev_err(&rspi->ctlr->dev, "transmit timeout\n");
                return ret;
            }
            for (i = 0; i < n; i++)
                rspi_write_data(rspi, *tx++);
​
            ret = rspi_wait_for_rx_full(rspi);
            if (ret < 0) {
                dev_err(&rspi->master->dev, "receive timeout\n");
                dev_err(&rspi->ctlr->dev, "receive timeout\n");
                return ret;
            }
            for (i = 0; i < n; i++)
                *rx++ = rspi_read_data(rspi);
        } else {
            ret = rspi_pio_transfer(rspi, tx, rx, n);
            if (ret < 0)
                return ret;
        }
        len -= n;
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                        xfer->rx_buf, xfer->len);
}
​
static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
{
    const u8 *tx = xfer->tx_buf;
    unsigned int n = xfer->len;
    unsigned int i, len;
    int ret;
​
    if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
    if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
        ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
        if (ret != -EAGAIN)
            return ret;
    }
​
    while (n > 0) {
        len = qspi_set_send_trigger(rspi, n);
        if (len == QSPI_BUFFER_SIZE) {
            ret = rspi_wait_for_tx_empty(rspi);
            if (ret < 0) {
                dev_err(&rspi->master->dev, "transmit timeout\n");
                dev_err(&rspi->ctlr->dev, "transmit timeout\n");
                return ret;
            }
            for (i = 0; i < len; i++)
                rspi_write_data(rspi, *tx++);
        } else {
            ret = rspi_pio_transfer(rspi, tx, NULL, len);
            if (ret < 0)
                return ret;
        }
        n -= len;
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    return 0;
}
​
static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
{
    u8 *rx = xfer->rx_buf;
    unsigned int n = xfer->len;
    unsigned int i, len;
    int ret;
​
    if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
    if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
        int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
        if (ret != -EAGAIN)
            return ret;
    }
​
    while (n > 0) {
        len = qspi_set_receive_trigger(rspi, n);
        if (len == QSPI_BUFFER_SIZE) {
            ret = rspi_wait_for_rx_full(rspi);
            if (ret < 0) {
                dev_err(&rspi->master->dev, "receive timeout\n");
                dev_err(&rspi->ctlr->dev, "receive timeout\n");
                return ret;
            }
            for (i = 0; i < len; i++)
                *rx++ = rspi_read_data(rspi);
        } else {
            ret = rspi_pio_transfer(rspi, NULL, rx, len);
            if (ret < 0)
                return ret;
        }
        n -= len;
    }
​
    return 0;
}
​
static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
                 struct spi_transfer *xfer)
static int qspi_transfer_one(struct spi_controller *ctlr,
                 struct spi_device *spi, struct spi_transfer *xfer)
{
    struct rspi_data *rspi = spi_master_get_devdata(master);
    struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
​
    if (spi->mode & SPI_LOOP) {
        return qspi_transfer_out_in(rspi, xfer);
    } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
        /* Quad or Dual SPI Write */
        return qspi_transfer_out(rspi, xfer);
    } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
        /* Quad or Dual SPI Read */
        return qspi_transfer_in(rspi, xfer);
    } else {
        /* Single SPI Transfer */
        return qspi_transfer_out_in(rspi, xfer);
    }
}
​
static int rspi_setup(struct spi_device *spi)
{
    struct rspi_data *rspi = spi_master_get_devdata(spi->master);
    struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
​
    rspi->max_speed_hz = spi->max_speed_hz;
​
    rspi->spcmd = SPCMD_SSLKP;
    if (spi->mode & SPI_CPOL)
        rspi->spcmd |= SPCMD_CPOL;
    if (spi->mode & SPI_CPHA)
        rspi->spcmd |= SPCMD_CPHA;
​
    /* CMOS output mode and MOSI signal from previous transfer */
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    }
    if (i) {
        /* Set final transfer data length and sequence length */
        rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
        rspi_write8(rspi, i - 1, RSPI_SPSCR);
    }
​
    return 0;
}
​
static int rspi_prepare_message(struct spi_master *master,
static int rspi_prepare_message(struct spi_controller *ctlr,
                struct spi_message *msg)
{
    struct rspi_data *rspi = spi_master_get_devdata(master);
    struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
    int ret;
​
    if (msg->spi->mode &
        (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
        /* Setup sequencer for messages with multiple transfer modes */
        ret = qspi_setup_sequencer(rspi, msg);
        if (ret < 0)
            return ret;
    }
​
    /* Enable SPI function in master mode */
    rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
    return 0;
}
​
static int rspi_unprepare_message(struct spi_master *master,
static int rspi_unprepare_message(struct spi_controller *ctlr,
                  struct spi_message *msg)
{
    struct rspi_data *rspi = spi_master_get_devdata(master);
    struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
​
    /* Disable SPI function */
    rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
​
    /* Reset sequencer for Single SPI Transfers */
    rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
    rspi_write8(rspi, 0, RSPI_SPSCR);
    return 0;
}
​
Show more
    ret = dmaengine_slave_config(chan, &cfg);
    if (ret) {
        dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
        dma_release_channel(chan);
        return NULL;
    }
​
    return chan;
}
​
static int rspi_request_dma(struct device *dev, struct spi_master *master,
static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr,
                const struct resource *res)
{
    const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
    unsigned int dma_tx_id, dma_rx_id;
​
    if (dev->of_node) {
        /* In the OF case we will get the slave IDs from the DT */
        dma_tx_id = 0;
        dma_rx_id = 0;
    } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
        dma_tx_id = rspi_pd->dma_tx_id;
        dma_rx_id = rspi_pd->dma_rx_id;
    } else {
        /* The driver assumes no error. */
        return 0;
    }
​
    master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
                           res->start + RSPI_SPDR);
    if (!master->dma_tx)
    ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
                         res->start + RSPI_SPDR);
    if (!ctlr->dma_tx)
        return -ENODEV;
​
    master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
                           res->start + RSPI_SPDR);
    if (!master->dma_rx) {
        dma_release_channel(master->dma_tx);
        master->dma_tx = NULL;
    ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
                         res->start + RSPI_SPDR);
    if (!ctlr->dma_rx) {
        dma_release_channel(ctlr->dma_tx);
        ctlr->dma_tx = NULL;
        return -ENODEV;
    }
​
    master->can_dma = rspi_can_dma;
    ctlr->can_dma = rspi_can_dma;
    dev_info(dev, "DMA available");
    return 0;
}
​
static void rspi_release_dma(struct spi_master *master)
static void rspi_release_dma(struct spi_controller *ctlr)
{
    if (master->dma_tx)
        dma_release_channel(master->dma_tx);
    if (master->dma_rx)
        dma_release_channel(master->dma_rx);
    if (ctlr->dma_tx)
        dma_release_channel(ctlr->dma_tx);
    if (ctlr->dma_rx)
        dma_release_channel(ctlr->dma_rx);
}
​
static int rspi_remove(struct platform_device *pdev)
{
    struct rspi_data *rspi = platform_get_drvdata(pdev);
​
    rspi_release_dma(rspi->master);
    rspi_release_dma(rspi->ctlr);
    pm_runtime_disable(&pdev->dev);
​
    return 0;
}
​
static const struct spi_ops rspi_ops = {
    .set_config_register =  rspi_set_config_register,
    .transfer_one =     rspi_transfer_one,
    .mode_bits =        SPI_CPHA | SPI_CPOL | SPI_LOOP,
    .flags =        SPI_MASTER_MUST_TX,
    .flags =        SPI_CONTROLLER_MUST_TX,
    .fifo_size =        8,
};
​
static const struct spi_ops rspi_rz_ops = {
    .set_config_register =  rspi_rz_set_config_register,
    .transfer_one =     rspi_rz_transfer_one,
    .mode_bits =        SPI_CPHA | SPI_CPOL | SPI_LOOP,
    .flags =        SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
    .flags =        SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
    .fifo_size =        8,  /* 8 for TX, 32 for RX */
};
​
static const struct spi_ops qspi_ops = {
    .set_config_register =  qspi_set_config_register,
    .transfer_one =     qspi_transfer_one,
    .mode_bits =        SPI_CPHA | SPI_CPOL | SPI_LOOP |
                SPI_TX_DUAL | SPI_TX_QUAD |
                SPI_RX_DUAL | SPI_RX_QUAD,
    .flags =        SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
    .flags =        SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
    .fifo_size =        32,
};
​
#ifdef CONFIG_OF
static const struct of_device_id rspi_of_match[] = {
    /* RSPI on legacy SH */
    { .compatible = "renesas,rspi", .data = &rspi_ops },
    /* RSPI on RZ/A1H */
    { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
    /* QSPI on R-Car Gen2 */
    { .compatible = "renesas,qspi", .data = &qspi_ops },
    { /* sentinel */ }
};
​
MODULE_DEVICE_TABLE(of, rspi_of_match);
​
static int rspi_parse_dt(struct device *dev, struct spi_master *master)
static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
{
    u32 num_cs;
    int error;
​
    /* Parse DT properties */
    error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
    if (error) {
        dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
        return error;
    }
​
    master->num_chipselect = num_cs;
    ctlr->num_chipselect = num_cs;
    return 0;
}
#else
#define rspi_of_match   NULL
static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
{
    return -EINVAL;
}
#endif /* CONFIG_OF */
​
static int rspi_request_irq(struct device *dev, unsigned int irq,
                irq_handler_t handler, const char *suffix,
                void *dev_id)
{
    const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
                      dev_name(dev), suffix);
    if (!name)
        return -ENOMEM;
​
    return devm_request_irq(dev, irq, handler, 0, name, dev_id);
}
​
static int rspi_probe(struct platform_device *pdev)
{
    struct resource *res;
    struct spi_master *master;
    struct spi_controller *ctlr;
    struct rspi_data *rspi;
    int ret;
    const struct rspi_plat_data *rspi_pd;
    const struct spi_ops *ops;
​
    master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
    if (master == NULL)
    ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
    if (ctlr == NULL)
        return -ENOMEM;
​
    ops = of_device_get_match_data(&pdev->dev);
    if (ops) {
        ret = rspi_parse_dt(&pdev->dev, master);
        ret = rspi_parse_dt(&pdev->dev, ctlr);
        if (ret)
            goto error1;
    } else {
        ops = (struct spi_ops *)pdev->id_entry->driver_data;
        rspi_pd = dev_get_platdata(&pdev->dev);
        if (rspi_pd && rspi_pd->num_chipselect)
            master->num_chipselect = rspi_pd->num_chipselect;
            ctlr->num_chipselect = rspi_pd->num_chipselect;
        else
            master->num_chipselect = 2; /* default */
            ctlr->num_chipselect = 2; /* default */
    }
​
    /* ops parameter check */
    if (!ops->set_config_register) {
        dev_err(&pdev->dev, "there is no set_config_register\n");
        ret = -ENODEV;
        goto error1;
    }
​
    rspi = spi_master_get_devdata(master);
    rspi = spi_controller_get_devdata(ctlr);
    platform_set_drvdata(pdev, rspi);
    rspi->ops = ops;
    rspi->master = master;
    rspi->ctlr = ctlr;
​
    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
    rspi->addr = devm_ioremap_resource(&pdev->dev, res);
    if (IS_ERR(rspi->addr)) {
        ret = PTR_ERR(rspi->addr);
        goto error1;
    }
​
    rspi->clk = devm_clk_get(&pdev->dev, NULL);
    if (IS_ERR(rspi->clk)) {
        dev_err(&pdev->dev, "cannot get clock\n");
        ret = PTR_ERR(rspi->clk);
        goto error1;
    }
​
    pm_runtime_enable(&pdev->dev);
​
    init_waitqueue_head(&rspi->wait);
​
    master->bus_num = pdev->id;
    master->setup = rspi_setup;
    master->auto_runtime_pm = true;
    master->transfer_one = ops->transfer_one;
    master->prepare_message = rspi_prepare_message;
    master->unprepare_message = rspi_unprepare_message;
    master->mode_bits = ops->mode_bits;
    master->flags = ops->flags;
    master->dev.of_node = pdev->dev.of_node;
    ctlr->bus_num = pdev->id;
    ctlr->setup = rspi_setup;
    ctlr->auto_runtime_pm = true;
    ctlr->transfer_one = ops->transfer_one;
    ctlr->prepare_message = rspi_prepare_message;
    ctlr->unprepare_message = rspi_unprepare_message;
    ctlr->mode_bits = ops->mode_bits;
    ctlr->flags = ops->flags;
    ctlr->dev.of_node = pdev->dev.of_node;
​
    ret = platform_get_irq_byname(pdev, "rx");
    if (ret < 0) {
        ret = platform_get_irq_byname(pdev, "mux");
        if (ret < 0)
            ret = platform_get_irq(pdev, 0);
        if (ret >= 0)
            rspi->rx_irq = rspi->tx_irq = ret;
    } else {
        rspi->rx_irq = ret;
Show more
                       "rx", rspi);
        if (!ret)
            ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
                           rspi_irq_tx, "tx", rspi);
    }
    if (ret < 0) {
        dev_err(&pdev->dev, "request_irq error\n");
        goto error2;
    }
​
    ret = rspi_request_dma(&pdev->dev, master, res);
    ret = rspi_request_dma(&pdev->dev, ctlr, res);
    if (ret < 0)
        dev_warn(&pdev->dev, "DMA not available, using PIO\n");
​
    ret = devm_spi_register_master(&pdev->dev, master);
    ret = devm_spi_register_controller(&pdev->dev, ctlr);
    if (ret < 0) {
        dev_err(&pdev->dev, "spi_register_master error.\n");
        dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
        goto error3;
    }
​
    dev_info(&pdev->dev, "probed\n");
​
    return 0;
​
error3:
    rspi_release_dma(master);
    rspi_release_dma(ctlr);
error2:
    pm_runtime_disable(&pdev->dev);
error1:
    spi_master_put(master);
    spi_controller_put(ctlr);
​
    return ret;
}
​
static const struct platform_device_id spi_driver_ids[] = {
    { "rspi",   (kernel_ulong_t)&rspi_ops },
    { "rspi-rz",    (kernel_ulong_t)&rspi_rz_ops },
    { "qspi",   (kernel_ulong_t)&qspi_ops },
    {},
};
​
MODULE_DEVICE_TABLE(platform, spi_driver_ids);
​
#ifdef CONFIG_PM_SLEEP
static int rspi_suspend(struct device *dev)
{
    struct rspi_data *rspi = dev_get_drvdata(dev);
​
    return spi_master_suspend(rspi->master);
    return spi_controller_suspend(rspi->ctlr);
}
​
static int rspi_resume(struct device *dev)
{
    struct rspi_data *rspi = dev_get_drvdata(dev);
​
    return spi_master_resume(rspi->master);
    return spi_controller_resume(rspi->ctlr);
}
​
static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
#define DEV_PM_OPS  &rspi_pm_ops
#else
#define DEV_PM_OPS  NULL
#endif /* CONFIG_PM_SLEEP */
​
static struct platform_driver rspi_driver = {
    .probe =    rspi_probe,