Source
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#define SPRD_SPI_FIFO_SIZE 32
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#define SPRD_SPI_CHIP_CS_NUM 0x4
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#define SPRD_SPI_CHNL_LEN 2
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#define SPRD_SPI_DEFAULT_SOURCE 26000000
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#define SPRD_SPI_MAX_SPEED_HZ 48000000
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#define SPRD_SPI_AUTOSUSPEND_DELAY 100
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#define SPRD_SPI_DMA_STEP 8
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enum sprd_spi_dma_channel {
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SPI_RX,
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SPI_TX,
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SPI_MAX,
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SPRD_SPI_RX,
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SPRD_SPI_TX,
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SPRD_SPI_MAX,
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};
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struct sprd_spi_dma {
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bool enable;
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struct dma_chan *dma_chan[SPI_MAX];
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struct dma_chan *dma_chan[SPRD_SPI_MAX];
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enum dma_slave_buswidth width;
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u32 fragmens_len;
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u32 rx_len;
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};
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struct sprd_spi {
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void __iomem *base;
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phys_addr_t phy_base;
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struct device *dev;
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struct clk *clk;
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if (dma_submit_error(cookie))
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return dma_submit_error(cookie);
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dma_async_issue_pending(dma_chan);
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return 0;
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}
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static int sprd_spi_dma_rx_config(struct sprd_spi *ss, struct spi_transfer *t)
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{
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struct dma_chan *dma_chan = ss->dma.dma_chan[SPI_RX];
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struct dma_chan *dma_chan = ss->dma.dma_chan[SPRD_SPI_RX];
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struct dma_slave_config config = {
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.src_addr = ss->phy_base,
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.src_addr_width = ss->dma.width,
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.dst_addr_width = ss->dma.width,
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.dst_maxburst = ss->dma.fragmens_len,
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};
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int ret;
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ret = sprd_spi_dma_submit(dma_chan, &config, &t->rx_sg, DMA_DEV_TO_MEM);
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if (ret)
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return ret;
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return ss->dma.rx_len;
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}
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static int sprd_spi_dma_tx_config(struct sprd_spi *ss, struct spi_transfer *t)
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{
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struct dma_chan *dma_chan = ss->dma.dma_chan[SPI_TX];
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struct dma_chan *dma_chan = ss->dma.dma_chan[SPRD_SPI_TX];
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struct dma_slave_config config = {
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.dst_addr = ss->phy_base,
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.src_addr_width = ss->dma.width,
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.dst_addr_width = ss->dma.width,
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.src_maxburst = ss->dma.fragmens_len,
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};
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int ret;
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ret = sprd_spi_dma_submit(dma_chan, &config, &t->tx_sg, DMA_MEM_TO_DEV);
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if (ret)
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return ret;
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return t->len;
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}
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static int sprd_spi_dma_request(struct sprd_spi *ss)
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{
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ss->dma.dma_chan[SPI_RX] = dma_request_chan(ss->dev, "rx_chn");
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if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPI_RX])) {
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if (PTR_ERR(ss->dma.dma_chan[SPI_RX]) == -EPROBE_DEFER)
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return PTR_ERR(ss->dma.dma_chan[SPI_RX]);
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ss->dma.dma_chan[SPRD_SPI_RX] = dma_request_chan(ss->dev, "rx_chn");
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if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_RX])) {
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if (PTR_ERR(ss->dma.dma_chan[SPRD_SPI_RX]) == -EPROBE_DEFER)
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return PTR_ERR(ss->dma.dma_chan[SPRD_SPI_RX]);
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dev_err(ss->dev, "request RX DMA channel failed!\n");
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return PTR_ERR(ss->dma.dma_chan[SPI_RX]);
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return PTR_ERR(ss->dma.dma_chan[SPRD_SPI_RX]);
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}
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ss->dma.dma_chan[SPI_TX] = dma_request_chan(ss->dev, "tx_chn");
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if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPI_TX])) {
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if (PTR_ERR(ss->dma.dma_chan[SPI_TX]) == -EPROBE_DEFER)
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return PTR_ERR(ss->dma.dma_chan[SPI_TX]);
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ss->dma.dma_chan[SPRD_SPI_TX] = dma_request_chan(ss->dev, "tx_chn");
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if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_TX])) {
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if (PTR_ERR(ss->dma.dma_chan[SPRD_SPI_TX]) == -EPROBE_DEFER)
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return PTR_ERR(ss->dma.dma_chan[SPRD_SPI_TX]);
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dev_err(ss->dev, "request TX DMA channel failed!\n");
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dma_release_channel(ss->dma.dma_chan[SPI_RX]);
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return PTR_ERR(ss->dma.dma_chan[SPI_TX]);
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dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]);
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return PTR_ERR(ss->dma.dma_chan[SPRD_SPI_TX]);
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}
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return 0;
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}
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static void sprd_spi_dma_release(struct sprd_spi *ss)
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{
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if (ss->dma.dma_chan[SPI_RX])
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dma_release_channel(ss->dma.dma_chan[SPI_RX]);
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if (ss->dma.dma_chan[SPRD_SPI_RX])
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dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]);
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if (ss->dma.dma_chan[SPI_TX])
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dma_release_channel(ss->dma.dma_chan[SPI_TX]);
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if (ss->dma.dma_chan[SPRD_SPI_TX])
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dma_release_channel(ss->dma.dma_chan[SPRD_SPI_TX]);
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}
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static int sprd_spi_dma_txrx_bufs(struct spi_device *sdev,
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struct spi_transfer *t)
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{
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struct sprd_spi *ss = spi_master_get_devdata(sdev->master);
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u32 trans_len = ss->trans_len;
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int ret, write_size = 0;
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reinit_completion(&ss->xfer_completion);