Source
483
483
return 0;
484
484
}
485
485
486
486
static void ti_qspi_enable_memory_map(struct spi_device *spi)
487
487
{
488
488
struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
489
489
490
490
ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
491
491
if (qspi->ctrl_base) {
492
492
regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
493
-
MEM_CS_EN(spi->chip_select),
494
-
MEM_CS_MASK);
493
+
MEM_CS_MASK,
494
+
MEM_CS_EN(spi->chip_select));
495
495
}
496
496
qspi->mmap_enabled = true;
497
497
}
498
498
499
499
static void ti_qspi_disable_memory_map(struct spi_device *spi)
500
500
{
501
501
struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
502
502
503
503
ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
504
504
if (qspi->ctrl_base)
505
505
regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
506
-
0, MEM_CS_MASK);
506
+
MEM_CS_MASK, 0);
507
507
qspi->mmap_enabled = false;
508
508
}
509
509
510
510
static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
511
511
u8 data_nbits, u8 addr_width,
512
512
u8 dummy_bytes)
513
513
{
514
514
struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
515
515
u32 memval = opcode;
516
516