uboot-imx

MLK-17785 mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0

On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz.
We update DDR clock relevant settings to approach the target. But since the
limitation on LCDIF pix clock for HDMI output
(refer commit dba948539edd4611610d9f1fc3711d1d922262ae), we set DDR clock to
352.8Mhz (25.2Mhz * 14) by using the clock path:

	APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock

To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept,
so the divider 14 is calculated as:
	14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)

	NIC0_DIV:      1
	NIC1_DIV:      0
	LCDIF_PCC_DIV: 6

APLL and APLL PFD0 settings:

	PFD0 FRAC:  27
	APLL MULT:  22
	APLL NUM:   1
	APLL DENOM: 20

This patch applies the new settings for both DCD and plugin.
There is no DDR script change on this new frequency.
Overnight memtester is passed.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit a48daae2d43cb0415ad8b3cfca0f6d064ac6cd74)
(cherry picked from commit a3b6fff130f1cc1406d24fa534faa925beb2c87b)