uboot-imx

85xx: Fix the clock adjust of mpc8569mds board

Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.

Signed-off-by: Dave Liu <daveliu@freescale.com>