Commits
Jagan Teki committed 337fcdc06ba
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>