Commits
Prabhakar Kushwaha committed 6b50f62cc4d
board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>