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#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* power on board */
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
#define PCI_CHIP_VALLEYVIEW_2 0x0f32
#define PCI_CHIP_VALLEYVIEW_3 0x0f33
#define IS_830(dev) (dev == 0x3577)
#define IS_845(dev) (dev == 0x2562)
#define IS_85X(dev) (dev == 0x3582)
#define IS_865(dev) (dev == 0x2572)
#define IS_GEN2(dev) (IS_830(dev) || \
IS_845(dev) || \
IS_85X(dev) || \
IS_865(dev))
#define IS_PINEVIEW(dev) (dev == 0xa001 || \
dev == 0xa011)
#define IS_GEN3(dev) (IS_915(dev) || \
IS_945(dev) || \
IS_G33(dev) || \
IS_PINEVIEW(dev))
#define IS_I965GM(dev) (dev == 0x2A02)
#define IS_VALLEYVIEW(dev) (dev == 0xf30)
#define IS_VALLEYVIEW(dev) (((dev) == PCI_CHIP_VALLEYVIEW_PO) || \
((dev) == PCI_CHIP_VALLEYVIEW_1) || \
((dev) == PCI_CHIP_VALLEYVIEW_2) || \
((dev) == PCI_CHIP_VALLEYVIEW_3))
#define IS_GEN4(dev) (dev == 0x2972 || \
dev == 0x2982 || \
dev == 0x2992 || \
dev == 0x29A2 || \
dev == 0x2A02 || \
dev == 0x2A12 || \
dev == 0x2A42 || \
dev == 0x2E02 || \
dev == 0x2E12 || \