linux-phytec-fsl

powerpc: Add fsl mpic timer binding

Update the existing example in the general mpic binding to have a
separate TCRx region.  Currently the example doesn't describe TCRx at
all.  The one upstream device tree with an mpic timer node (p1022ds)
uses one large reg region to describe both, even though there are other
unrelated registers in between.  That device tree also contains a bogus
interrupt specifier, and there's no upstream software that uses this yet,
so changing this shouldn't be a problem.

Add a full binding for the MPIC timer node, not just an example of
4-cell interrupts in the MPIC binding.

Add fsl,available-ranges, similar to msi-available-ranges.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>