uboot-phytec
Public
Source
committed fd40ad0d579x
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6if ARCH_SUNXIconfig SPL_LDSCRIPT default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64config IDENT_STRING default " Allwinner Technology"config DRAM_SUN4I bool help Select this dram controller driver for Sun4/5/7i platforms, like A10/A13/A20.config DRAM_SUN6I bool help Select this dram controller driver for Sun6i platforms, like A31/A31s.config DRAM_SUN8I_A23 bool help Select this dram controller driver for Sun8i platforms, for A23 SOC.config DRAM_SUN8I_A33 bool help Select this dram controller driver for Sun8i platforms, for A33 SOC.config DRAM_SUN8I_A83T bool help Select this dram controller driver for Sun8i platforms, for A83T SOC.config DRAM_SUN9I bool help Select this dram controller driver for Sun9i platforms, like A80.config DRAM_SUN50I_H6 bool help Select this dram controller driver for some sun50i platforms, like H6.config SUN6I_P2WI bool "Allwinner sun6i internal P2WI controller" help If you say yes to this option, support will be included for the P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi SOCs. The P2WI looks like an SMBus controller (which supports only byte accesses), except that it only supports one slave device. This interface is used to connect to specific PMIC devices (like the AXP221).config SUN6I_PRCM bool help Support for the PRCM (Power/Reset/Clock Management) unit available in A31 SoC.config AXP_PMIC_BUS bool "Sunxi AXP PMIC bus access helpers" help Select this PMIC bus access helpers for Sunxi platform PRCM or other AXP family PMIC devices.config SUN8I_RSB bool "Allwinner sunXi Reduced Serial Bus Driver" help Say y here to enable support for Allwinner's Reduced Serial Bus (RSB) support. This controller is responsible for communicating with various RSB based devices, such as AXP223, AXP8XX PMICs, and AC100/AC200 ICs.config SUNXI_SRAM_ADDRESS hex default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 default 0x20000 if MACH_SUN50I_H6 default 0x0 ---help--- Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, with the first SRAM region being located at address 0. Some newer SoCs map the boot ROM at address 0 instead and move the SRAM to a different address.