uboot-phytec

// SPDX-License-Identifier: GPL-2.0+

/*

 * Sun8i a33 platform dram controller init.

 *

 * (C) Copyright 2007-2015 Allwinner Technology Co.

 *                         Jerry Wang <wangflord@allwinnertech.com>

 * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>

 * (C) Copyright 2015      Hans de Goede <hdegoede@redhat.com>

 */

#include <common.h>

#include <errno.h>

#include <asm/io.h>

#include <asm/arch/clock.h>

#include <asm/arch/dram.h>

#include <asm/arch/prcm.h>

​

/* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */

#define DRAM_CLK_MUL 2

#define DRAM_CLK_DIV 4

#define DRAM_SIGMA_DELTA_ENABLE 1

​

struct dram_para {

    u8 cs1;

    u8 seq;

    u8 bank;

    u8 rank;

    u8 rows;

    u8 bus_width;

    u16 page_size;

};

​

static void mctl_set_cr(struct dram_para *para)

{

    struct sunxi_mctl_com_reg * const mctl_com =

            (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;

​

    writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |

           MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |

           (para->seq ? MCTL_CR_SEQUENCE : 0) |

           ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |

           MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |

           MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),

           &mctl_com->cr);

}

​

static void auto_detect_dram_size(struct dram_para *para)

{

    u8 orig_rank = para->rank;

    int rows, columns;

​

    /* Row detect */

    para->page_size = 512;

    para->seq = 1;

    para->rows = 16;

    para->rank = 1;

    mctl_set_cr(para);

    for (rows = 11 ; rows < 16 ; rows++) {

        if (mctl_mem_matches(1 << (rows + 9))) /* row-column */

            break;

    }

​

    /* Column (page size) detect */

    para->rows = 11;

    para->page_size = 8192;

    mctl_set_cr(para);

    for (columns = 9 ; columns < 13 ; columns++) {

        if (mctl_mem_matches(1 << columns))

            break;

    }

​

    para->seq = 0;

    para->rank = orig_rank;

    para->rows = rows;

    para->page_size = 1 << columns;

    mctl_set_cr(para);

}

​

static inline int ns_to_t(int nanoseconds)

{

    const unsigned int ctrl_freq =

        CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;

​

    return (ctrl_freq * nanoseconds + 999) / 1000;

}

​

static void auto_set_timing_para(struct dram_para *para)

{

    struct sunxi_mctl_ctl_reg * const mctl_ctl =

        (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;

    u32 reg_val;

​

    u8 tccd     = 2;