uboot-phytec

/*************** DEFINES for Intel StrataFlash FLASH chip ********************/

​

/*

 * acceptable chips types are:

 *

 *  28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A

 */

​

/* register addresses, valid only following an CHIP_CMD_RD_ID command */

#define CHIP_ADDR_REG_MAN   0x000000    /* manufacturer's id */

#define CHIP_ADDR_REG_DEV   0x000001    /* device id */

#define CHIP_ADDR_REG_CFGM  0x000003    /* master lock config */

#define CHIP_ADDR_REG_CFG(b)    (((b)<<16)|2)   /* lock config for block b */

​

/* Commands */

#define CHIP_CMD_RST        0xFF        /* reset flash */

#define CHIP_CMD_RD_ID      0x90        /* read the id and lock bits */

#define CHIP_CMD_RD_QUERY   0x98        /* read device capabilities */

#define CHIP_CMD_RD_STAT    0x70        /* read the status register */

#define CHIP_CMD_CLR_STAT   0x50        /* clear the staus register */

#define CHIP_CMD_WR_BUF     0xE8        /* clear the staus register */

#define CHIP_CMD_PROG       0x40        /* program word command */

#define CHIP_CMD_ERASE1     0x20        /* 1st word for block erase */

#define CHIP_CMD_ERASE2     0xD0        /* 2nd word for block erase */

#define CHIP_CMD_ERASE_SUSP 0xB0        /* suspend block erase */

#define CHIP_CMD_LOCK       0x60        /* 1st word for all lock cmds */

#define CHIP_CMD_SET_LOCK_BLK   0x01        /* 2nd wrd set block lock bit */

#define CHIP_CMD_SET_LOCK_MSTR  0xF1        /* 2nd wrd set master lck bit */

#define CHIP_CMD_CLR_LOCK_BLK   0xD0        /* 2nd wrd clear blk lck bit */

​

/* status register bits */

#define CHIP_STAT_DPS       0x02        /* Device Protect Status */

#define CHIP_STAT_VPPS      0x08        /* VPP Status */

#define CHIP_STAT_PSLBS     0x10        /* Program+Set Lock Bit Stat */

#define CHIP_STAT_ECLBS     0x20        /* Erase+Clr Lock Bit Stat */

#define CHIP_STAT_ESS       0x40        /* Erase Suspend Status */

#define CHIP_STAT_RDY       0x80        /* WSM Mach Status, 1=rdy */

​

#define CHIP_STAT_ERR       (CHIP_STAT_VPPS | CHIP_STAT_DPS | \

                    CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)

​

/* ID and Lock Configuration */

#define CHIP_RD_ID_LOCK     0x01        /* Bit 0 of each byte */

#define CHIP_RD_ID_MAN      0x89        /* Manufacturer code = 0x89 */

#define CHIP_RD_ID_DEV      CFG_FLASH_ID

​

/* dimensions */

#define CHIP_WIDTH      2       /* chips are in 16 bit mode */

#define CHIP_WSHIFT     1       /* (log2 of CHIP_WIDTH) */

#define CHIP_NBLOCKS        CFG_FLASH_NBLOCKS

#define CHIP_BLKSZ      (128 * 1024)    /* of 128Kbytes each */

#define CHIP_SIZE       (CHIP_BLKSZ * CHIP_NBLOCKS)

​

/********************** DEFINES for Hymod Flash ******************************/

​

/*

 * The hymod board has 2 x 28F320J5 chips running in

 * 16 bit mode, for a 32 bit wide bank.

 */

​

typedef unsigned long bank_word_t;      /* 8/16/32/64bit unsigned int */

typedef volatile bank_word_t *bank_addr_t;

typedef unsigned long bank_size_t;      /* want this big - >= 32 bit */